Resource shared architecture of multiple transforms for multiple video codecs

Wahid, Khan A.; Martuza, Muhammad; Das, Mousumi; McCrosky, Carl

doi:10.1109/ccece.2011.6030599

Cited by 8 publications

(11 citation statements)

References 5 publications

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“…• The proposed 2-D DCT/IDCT architecture supports a greater number of standards than do the methods proposed in [14][15][16][17], [18][19][20]. Wahid [15] Qi [16] Kim [17] Fan [12] Lee [18] Huang [19] Madisetti [20] Proposed • The proposed architecture provides superior hardware efficiency than that offered by existing schemes.…”

Section: Comparison With Existing Methodsmentioning

confidence: 99%

“…Table II presents a comparison of the proposed and existing methods. In [14], Martuza et al [15]. That architecture is based on new multidimensional delta mapping, and the IDCT of AVS has the lowest computational unit to compute the IDCTs of the other four codecs.…”

Section: Comparison With Existing Methodsmentioning

confidence: 99%

“…Wahid et al presented a resource-sharing architecture of multiple transforms capable of supporting five video codecs (H.264, JPEG, MPEG-2, VC-1, and AVS)[15]. DCT, discrete cosine transform; IDCT, inverse discrete cosine transform.…”

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confidence: 99%

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Low‐cost multi‐standard simultaneous forward and inverse video transform core

Tseng

Chen

Kao

et al. 2015

Circuit Theory & Apps

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This paper presents a cost-effective, two-dimensional (2-D) discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) capable of MPEG1/2/4, H.264 4 × 4/8 × 8, and VC-1 4 × 4/8 × 8/4 × 8/8 × 4 standards. We developed multilevel factor sharing in conjunction with distributed arithmetic in a scheme referred to as common sharing distributed arithmetic to enable sharing of the coefficient matrix circuit and replace multipliers with adders and shifters. By taking advantage of the similarities between DCT and IDCT transforms, we were able to implement an interlaced sorting method in a single circuit of the DCT and IDCT transform core in order to reduce area overhead while enabling the simultaneous operation of DCT and IDCT. The proposed design arranges the data of the first dimension and second dimension in order to reuse the same 1-D core to compute 2-D data. In this manner, first dimension and second dimension data of DCT and IDCT can be processed simultaneously in a single transform core. The efficacy of the proposed approach has been verified by fabricating a test chip using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm complementary metal-oxide semiconductor process. The inverse transform core was shown to have an operating frequency of 227 MHz and throughput of 454 Mpel/s with a gate count of 32.5 k. Figure 4. Time scheduling of proposed SORT1 circuit for N = 8. 1st-D, first-dimensional; 2nd-D, seconddimensional; DCT, discrete cosine transform; IDCT, inverse discrete cosine transform. 1582 Y.-H. TSENG ET AL.

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Section: Comparison With Existing Methodsmentioning

confidence: 99%

Section: Comparison With Existing Methodsmentioning

confidence: 99%

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Low‐cost multi‐standard simultaneous forward and inverse video transform core

Tseng

Chen

Kao

et al. 2015

Circuit Theory & Apps

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“…Therefore, the application domain of this processing structure is limited to the design of high-performance decoders, being unsuitable to implement video encoders. This characteristic is common to many of the designs enumerated in Table 6, since they are able to compute only a subset of the transforms defined in one or multiple video standards [23,24,26,28,29,33]. In fact, to the best of the authors' knowledge, the MST architecture herein proposed is one of the first structures that is able to compute the complete set of transforms adopted in the AVC, AVS, VC-1 and HEVC standards.…”

Section: Comparative Analysismentioning

confidence: 99%

“…Some of these designs were even derived by jointly optimizing the algorithms of the considered set http://asp.eurasipjournals.com/content/2014/1/108 of transforms using different techniques (e.g. matrix factorizations [19], matrix decompositions [32] and 1-D delta matrix mapping [33]). …”

Section: Related Workmentioning

confidence: 99%

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

Dias

Roma

Sousa

2014

EURASIP J. Adv. Signal Process.

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A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e.g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 × 4,320 at 30 fps) in real time.

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Multi-transform 2D DCT Architecture Supporting AVC and HEVC Video Codec

Sai

Mamatha

2022

Advances in Data Computing, Communication and Security

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Resource shared architecture of multiple transforms for multiple video codecs

Cited by 8 publications

References 5 publications

Low‐cost multi‐standard simultaneous forward and inverse video transform core

Low‐cost multi‐standard simultaneous forward and inverse video transform core

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

Multi-transform 2D DCT Architecture Supporting AVC and HEVC Video Codec

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