“…Here are the simulation results of the SUM, CONS, ANY, 3 input ternary adder, 4 input ternary adderand 4*4 Ternary Multiplier built with 32nm CNTFET technology. [4], [5], [6] respectively.The power of proposed design is same as [5] but the delay is reduced to 90%.The is PDP of proposed system is reduced by 99.62%, 98 %, 94.88%, 94.2% ,90%,82.12% in comparison with [1], [2], [3], [4], [5], [6] respectively.…”