RETRACTED ARTICLE: Performance improvement of elliptic curve cryptography system using low power, high speed 16 × 16 Vedic multiplier based on reversible logic

Karthikeyan, S. Prabhakar; Jagadeeswari, M.

doi:10.1007/s12652-020-01795-5

Cited by 14 publications

(3 citation statements)

References 14 publications

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“…Algorithms comprised different key types that are effectively employed to implement for encryptiondecryption process [6]. Single key is worn for the encryption and decryption function in symmetric crypto procedure [7]. Moreover, in the asymmetric crypto model, double keys were employed to process the crypto functions [8].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique

Srik¹,

Ravindra²,

Ramakrishna

et al. 2023

Wireless Pers Commun

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The threat application has been increased a lot in the digital application; hence, protecting the data and the digital application is very important. Several crypto algorithms were already implemented with different sub-module to secure the data from the malicious event. However, the harmfulness of the malicious events has broken the security in many cases. This has resulted in high data theft, less con dential range and data loss So, the present article has designed a novel Bernoulli Data-encryptionstandard (B-DES) for securing the digital communication in the wireless environment. Here, the Bernoulli function has been performed after the XOR process, and then during the decryption process, the function of the novel B-DES has been reversed. Moreover, the designed encryption approach is checked with the brute force attack. Here, the gained power usage by the designed scheme is 193 mW, compared to other models; it has diminished the power usage by 7%. Moreover, the earned memory utilization is 0.6 kB, compared to other compared models, it has reduced the memory utilization is 3%. The delay rated recorded by the designed model is 3.43 ns, compared to other models it has minimized the delay score by 3%.

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique

Srik¹,

Ravindra²,

Ramakrishna

et al. 2023

Wireless Pers Commun

View full text Add to dashboard Cite

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“…There are a bewildering variety of methods used to build multipliers for unsigned values, each with advantages and disadvantages [1]. High-speed multipliers have become increasingly vital in modern architecture design, and scientists are still exploring various ways to speed up the operation of these foundational components [2]. Computer and signal processing applications have increased high-speed processing.…”

Section: Introductionmentioning

confidence: 99%

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Kalaiselvi,

Sabeenian

2024

Analog Integr Circ Sig Process

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Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for the FPGA implementation employing VLSI design approaches and parallel computing technology. Signal processing, machine learning, and recon gurable computing research should be closely monitored as arti cial intelligence develops. To enable deep learning algorithms, continued research should be done on energy-constrained computing technology. Multipliers and adders are key components of deep learning algorithms. The multiplier is an energy-intensive component of signal processing in ALU, Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). For the DNN, this method introduces the Booth multiplier blocks and the carry-save multiplier in the Anurupyena architecture. Traditional multiplication methods like the array multiplier, Wallace multiplier, and Booth multiplier are contrasted with the Vedic mathematics algorithms. On a speci c hardware platform, Vedic algorithms perform faster, use less power, and take up less space. Implementations were carried out using Verilog HDL and Xilinx Vivado 2019.1 on Kintex-7. The area and propagation delay were reduced compared to other multiplier architectures.

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“…Binary multipliers play a significant role in microprocessor systems [Karthikeyan and Jagadeeswari, 2021][Kamrani and Heikalabad, 2021][Balasubramanian et al, 2021. They are considered one of the critical components when it comes to performance in various kinds of Embedded Components, Digital Signals Processors, and Logical Units that execute different applications such as image processing, arithmetic, and filtering.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

Al-Nounou¹,

Al-Khaleel²,

Obeidat³

et al. 2022

jucs

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Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

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RETRACTED ARTICLE: Performance improvement of elliptic curve cryptography system using low power, high speed 16 × 16 Vedic multiplier based on reversible logic

Cited by 14 publications

References 14 publications

Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique

Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

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