Reversible and DNA Computing 2020
DOI: 10.1002/9781119679455.ch1
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Reversible Logic Synthesis

Gerhard W. Dueck
1
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Dmitri Maslov
2
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Cited by 18 publications
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References 40 publications
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A New Generalized Reconfigurable Architecture for Digital Signal Processor

James
1
,
Shahana
2
,
Jacob
3
et al. 2007
15th International Conference on Advanced Computing and Communications (ADCOM 2007)
1
0
0
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A New Generalized Reconfigurable Architecture for Digital Signal Processor

James
1
,
Shahana
2
,
Jacob
3
et al. 2007
15th International Conference on Advanced Computing and Communications (ADCOM 2007)
1
0
0
0
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Design of reversible 32-bit BCD add-subtract unit using parallel pipelined method

Anjana1,
AnanthaLakshmi
2
2016
2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEIC
1
0
0
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The Reversible Network Cascade Based on Reversible Logic Gate Coding Method

Li
1
,
Guan
2
,
Chen
3
et al. 2009
2009 Fifth International Conference on Information Assurance and Security
0
0
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