Review of Leakage Power Reduction in CMOS Circuits

Abstract

Recent Technological advances in Wireless Communication has shown the convergence of terminals and networks that support multimedia and real-time applications. This obviously puts an immense pressure on battery of any mobile device. The CMOS has been the leading technology in today's world of mobile communication due to its low power consumption. Reduction of leakage power in CMOS has been the research interest for the last couple of years. In CMOS integrated circuit design there is an important trade-off between technology scaling and static power consumption. In today's CMOS technology the leakage power consumption plays a significant role. As we approaching to nano-scale design the total chip power consumption becomes dependent on leakage power. Increasing the battery life in mobile wireless communication and mobile computing and similar other applications is the topic of research now-a days... Further, since the leakage of battery exists even when devices are in idle state makes leakage power loss most critical in CMOS VLSI circuits. Many techniques have been evolved to tackle the problem and its still in progress. This paper mainly focuses on the review of various works done in this field till today's date. Further a review of recent work done on a new technique LSSR (Lector Stack State Retention Technique) is discussed in the paper.

Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors

“…The voltage drop across R has two implications. Due to this bodily impact, the resistance value of LVT quick release transistors is raised due to a decrease in Vdd power rating and a rise in Vdd-Vx bodily impact pushing power [11] [12]. Consequently, the circuitry's resistor ought to have been minimal and the sleep transistors big in order to minimise those impacts.…”

Study on Leakage Current Reduction Technique in VLSI Design

“…In CMOS nanoscale technology several methods are originated to overcome the problem of leakage in CMOS circuits [11].…”

“…This method utilizes the sleep strategy and is one of the most frequently recognized outdated techniques for the decreasing of the sub-threshold leakage energy [15]. Additional transistors (sleep transistors) remain injected into the Power supply and Ground in this method [11].…”

“…Leakage power can therefore be effectively bridged by shutting off the energy biasing. Such techniques are called gated-VDD and gated-GND [11].…”

“…Here Leakage Control Transistor (LECTOR) technique was illustrated by the scenario of a NAND gate. A CMOS NAND gate with double-leakage transistor accumulation was proposed in reference [11].…”