Review of memristor devices in neuromorphic computing: materials sciences and device challenges

Li, Yibo; Wang, Zhongrui; Midya, Rivu; Xia, Qiangfei; Yang, J. Joshua

doi:10.1088/1361-6463/aade3f

Cited by 418 publications

(280 citation statements)

References 82 publications

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“…The arrows of Figure 6 represent the current flowing through a chosen memristor in case of write, erase, and read processes. Notably, there are non-idealities such as sneak currents and wire resistance in array-level, which could degrade the performance of neuromorphic computing [35,44,[58][59][60]. The sneak currents affect learning accuracy and epochs because of undesired information, especially large-scale array.…”

Section: Neuromorphic Systems Based On Crossbar Array Of Memristor Symentioning

confidence: 99%

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Memristor Synapses for Neuromorphic Computing

Choi¹,

Ham²

2019

Memristors - Circuits and Applications of Memristor Devices [Working Title]

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Neuromorphic computing, which imitates the principle behind biological synapses with a high degree of parallelism, has recently emerged as a promising candidate for novel and sustainable computing technologies. The first step toward realizing a massively parallel neuromorphic system is to develop an artificial synapse capable of emulating synapse functionality, such as analog modulation, with ultralow power consumption and robust controllability. We begin this chapter with a simple description of neuromorphic systems and memristor synapses. Further, we introduce and evaluate the state-of-the-art neuromorphic hardware technology in terms of novel functional materials and device architectures toward the implementation of fully neuromorphic computers, which have been extensively explored in recent years. Finally, we briefly describe artificial neural networks based on memristor synapse in forms of crossbar arrays.Conventional computing architecture, that is, von Neumann architecture, forms the groundwork for modern computing technologies [3,18]. Despite tremendous growth in computing performance, classical architecture currently suffers from the von Neumann bottleneck, which results from data movements between the processor and the memory unit [4,5]. The memory wall issue, causing high power consumption and low speed, hinders the continuous development of computing technologies [4,5,9]. Moreover, artificial neural network (ANN) algorithms, such as deep learning [19], deal with image classification [20,21], sound recognition [22,23], specific complex tasks (e.g., the AlphaGo [24]) and so on. Although the ANN algorithms have exhibited superior performance over the conventional computing technologies, they are, at present, constructed on the von Neumann architecture; hence, considerable time and energy resources are required for their operation [8,9]. Neuromorphic architecture [6,7], a bio-inspired computing architecture, is one of the most promising candidates to resolve these problems. The neuromorphic systems take advantage of the cerebral nervous system, which consists of a massive parallel connectivity between the neurons (i.e., processor) and the synapses (i.e., memory), indicating the absence of the von Neumann bottleneck [8,9]. Figure 1 shows the shift of the computing architecture from von Neumann architecture (Figure 1a) to neuromorphic architecture (Figure 1b). The von Neumann architecture shows that the processor and memory are separate, leading to the von Neumann bottleneck. In contrast, in the case of neuromorphic architecture, the neurons and synapses are combined, alleviating the bottleneck issue. The neurons are uncomplicated computing units, the synapses are local memory units, and the communication channels (red line) connect numerous neurons and synapses. It should be noted that the practical purpose of neuromorphic systems is not to replace the von Neumann architecture completely, but to supplement the conventional architecture to make up its leeway, especially for intelligent tasks such as image r...

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Section: Neuromorphic Systems Based On Crossbar Array Of Memristor Symentioning

confidence: 99%

“…This influences output currents, leading to degradation of learning performance. The non-idealities in array-level could be overcome by device functions [35,44], operational scheme [39,[58][59][60], or learning algorithms [35,[40][41][42][43][44] to some degree.…”

Section: Neuromorphic Systems Based On Crossbar Array Of Memristor Symentioning

confidence: 99%

Memristor Synapses for Neuromorphic Computing

Choi¹,

Ham²

2019

Memristors - Circuits and Applications of Memristor Devices [Working Title]

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“…A synaptic device in a crossbar array based analog hardware NN must have several conductance states that can be controlled electrically to store and update the weight values of the NN. Several Non Volatile Memory (NVM) devices like floating gate transistors, chalcogenide based Phase Change Memory (PCM) devices, oxide based Resistive Random Access Memory (RRAM) devices and spintronic devices have been proposed and used as synaptic devices in previous implementations of analog hardware NN [5,6,7,13,14,15,16,17,18,19]. However, these NVM devices have several issues associated with them with respect to achieving on-chip learning in crossbar arrays made of them.…”

Section: Introductionmentioning

confidence: 99%

“…Floating gate transistor synapses need high voltage pulses for weight update and have low endurance [19,20,21,22,23,24]. Memristive oxide based Resistive Random Access Memory (RRAM) devices and Phase Change Memory (PCM) devices [16,17,18] exhibit an asymmetric/unipolar and non-linear dependence between conductance (and weight) update and programming pulses, which affects the accuracy during on-chip learning of crossbar arrays that use such devices [5,25,26,27]. Moreover, for fabricating RRAM, PCM or spintronic device based hardware NN systems [5,7,28], dedicated in-house fabrication facilities are needed since they involve novel materials.…”

Section: Introductionmentioning

confidence: 99%

“…9) [29]. In Section 5, we next compare the speed and energy performance of our transistor synapse based analog NN against analog implementations of the same through previously proposed NVM devices with respect to on-chip learning on the exact same dataset [17,25,30,49,31]. Speed and energy consumption are almost equal for our proposed transistor synapse and spintronic (domain wall based) synapse (Table I).…”

Section: Introductionmentioning

confidence: 99%

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On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network

Dey

Sharda

Saxena

et al. 2019

2019 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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On-chip learning in a crossbar array based analog hardware Neural Network (NN) has been shown to have major advantages in terms of speed and energy compared to training NN on a traditional computer. However analog hardware NN proposals and implementations thus far have mostly involved Non Volatile Memory (NVM) devices like Resistive Random Access Memory (RRAM), Phase Change Memory (PCM), spintronic devices or floating gate transistors as synapses. Fabricating systems based on RRAM, PCM or spintronic devices need in-house laboratory facilities and cannot be done through merchant foundries, unlike conventional silicon based CMOS chips. Floating gate transistors need large voltage pulses for weight update, making on-chip learning in such systems energy inefficient. This paper proposes and implements through SPICE simulations on-chip learning in analog hardware NN using only conventional silicon based MOSFETs (without any floating gate) as synapses. We first model the synaptic characteristic of our single transistor synapse using SPICE circuit simulator and benchmark it against experimentally obtained current-voltage characteristics of a transistor. Next we design a Fully Connected Neural Network (FCNN) crossbar array using such transistor synapses. We also design analog peripheral circuits for neuron and synaptic weight update calculation, needed for on-chip learning, again using conventional transistors. Simulating the entire system on SPICE circuit simulator, we obtain high training and test accuracy on the standard Fisher's Iris dataset, widely used in machine learning. We also account for device variability and noise in the circuit, and show that our circuit still trains on the given dataset. We also compare the speed and energy performance of our transistor based implementation of analog hardware NN with some previous implementations of NN with NVM devices and show comparable performance with respect to on-chip learning. Easy method of fabrication makes hardware NN using our proposed conventional silicon MOSFET really attractive for future implementations.

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Impact of Oxygen Non‐Stoichiometry on Near‐Ambient Temperature Ionic Mobility in Polaronic Mixed‐Ionic‐Electronic Conducting Thin Films

Defferriere

Kalaev

Rupp

et al. 2021

Adv Funct Materials

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Enhanced ionic mobility in mixed ionic and electronic conducting solids contributes to improved performance of memristive memory, energy storage and conversion, and catalytic devices. Ionic mobility can be significantly depressed at reduced temperatures, for example, due to defect association and therefore needs to be monitored. Measurements of ionic transport in mixed conductors, however, proves to be difficult due to dominant electronic conductivity. This study examines the impact of different levels of quenched-in oxygen deficiency on the oxygen vacancy mobility near room temperature. A praseodymium doped ceria (Pr 0.1 Ce 0.9 O 2-δ) film is grown by pulsed laser deposition and annealed in various oxygen partial pressures to modify its oxygen vacancy concentration. Changes in film non-stoichiometry are monitored by tracking the optical absorption related to the oxidation state of Pr ions. A 13-fold increase in ionic mobility at 60 °C for increases in oxygen non-stoichiometry from 0.032 to 0.042 is detected with negligible changes in migration enthalpy and large changes in pre-factor. Several factors potentially contributing to the large pre-factor changes are examined and discussed. Insights into how ionic defect concentration can markedly impact ionic mobility should help in elucidating the origins of variations seen in nanoionic devices.

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Review of memristor devices in neuromorphic computing: materials sciences and device challenges

Cited by 418 publications

References 82 publications

Memristor Synapses for Neuromorphic Computing

Memristor Synapses for Neuromorphic Computing

On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network

Impact of Oxygen Non‐Stoichiometry on Near‐Ambient Temperature Ionic Mobility in Polaronic Mixed‐Ionic‐Electronic Conducting Thin Films

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