Robust focal-plane analog processing hardware for dynamic texture segmentation

Carmona-Galán

2011

Circuit Theory & Apps

SUMMARYThis paper addresses the design and VLSI implementation of MOS-based RC networks capable of performing time-controlled Gaussian filtering. In these networks, all the resistors are substituted one by one by a single MOS transistor biased in the ohmic region. The design of this elementary transistor is carefully realized according to the value of the ideal resistor to be emulated. For a prescribed signal range, the MOSFET in triode region delivers an interval of instantaneous resistance values. We demonstrate that, for the elementary 2-node network, establishing the design equation at a particular point within this interval guarantees minimum error. This equation is then corroborated for networks of arbitrary size by analysing them from a stochastic point of view. Following the design methodology proposed, the error committed by a MOS-based grid when compared to its equivalent ideal RC network is, despite the intrinsic nonlinearities of the transistors, below 1% even under mismatch conditions of 10%. In terms of image processing, this error hardly affects the outcome, which is perceptually equivalent to that of the ideal network. These results, extracted from simulation, are verified in a prototype vision chip with QCIF resolution manufactured in the AMS 0.35µm CMOS-OPTO process. This prototype incorporates a focal-plane MOS-based RC network which performs fully-programmable Gaussian filtering.

Section: On‐chip Gaussian Filteringmentioning

confidence: 99%

All‐MOS implementation of RC networks for time‐controlled Gaussian spatial filtering

Carmona-Galán

2011

Circuit Theory & Apps

“…3). Simulation using deviation parameters provided by the foundry is employed to confirm the minimization of the effect [16]. During the test of the chip no significant signs of anisotropy in the diffusion, due to time constant mismatch, has been appreciated.…”

Section: A Calibration Of the Time Constant For Diffusionmentioning

confidence: 99%

FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing

IEEE J. Solid-State Circuits

Carmona-Galán

Carranza-González

2011

Self Cite

This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image processing concurrently with photosensing. These processing elements can be grouped into fully-programmable rectangular-shape areas by loading the appropiate interconnection patterns into the registers at the edge of the array. The targeted processing can be thus performed block-wise. Readout is done pixel-by-pixel in a random access fashion. On-chip 8b ADC is provided. The image processing primitives implemented by the chip, experimentally tested and fully functional, are scale space and Gaussian pyramid generation, fully-programmable multiresolution scene representation -including foveation -and block-wise energy-based scene representation. The power consumption associated to the capture, processing and A/D conversion of an image flow at 30fps, with full-frame processing but reduced frame size output, ranges from 2.7mW to 5.6mW, depending on the operation to be performed.

“…The elementary cell of the analog core ( Fig. 11) was described in [18]. It contains a diffusion network built with p-type MOS transistors.…”

Section: Chip Description and Datamentioning

confidence: 99%

Focal-Plane Dynamic Texture Segmentation by Programmable Binning and Scale Extraction

Focal-Plane Sensor-Processor Chips

Carmona-Galán²

2011

Dynamic textures are spatially-repetitive time-varying visual patterns that present, however, some temporal stationarity within their constituting elements. In addition, their spatial and temporal extents are a priori unknown. This kind of patterns is very common in nature, therefore dynamic texture segmentation is an important task for surveillance and monitoring. Conventional methods employ optic flow computation though it represents a heavy computational load. Here we describe texture segmentation based on focal-plane space-scale generation. The programmable size of the subimages to be analyzed and the scales to be extracted encode sufficient information from the texture signature to warn its presence. A prototype smart imager has been designed and fabricated in 0.35µm CMOS, featuring a very lowpower scale-space representation of used-defined subimages.