Role of gate electrode in influencing interface trap sensitivity in SOI tunnel FETs

Abstract

This article reports the response of a silicon-on-insulator (SOI) TFET to the presence of semiconductor/ gate dielectric interface traps. A systematic strategy is designed keeping in view different parameters which are related to the gate of the device. Acceptor-like traps, and donor-like traps with Gaussian distribution are considered at the said interface for the entire analysis. Sensitivity % is taken as a figure of merit which measures the deviation of the drain current in presence of traps from the cases with no traps. The effect of temperature on interface traps, and the effect of interface traps on gate leakage current are analyzed. The acceptor-like traps are found to affect the on-state regime, and the donor-like traps are found to affect the ambipolar regime. Analyses on gate-drain underlap, gate-source overlap, shift of entire gate over the device, and gate work-function suggest that the gate electrode plays an important role in determining the sensitivity of the TFETs. Furthermore, noise spectral densities in presence of flicker, diffusion, and monopolar generation-recombination noise sources, and interface traps are reported.