ROM-less LNS

Ismail, Rizalafande Che; Coleman, J.N.

doi:10.1109/arith.2011.15

Cited by 26 publications

(11 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several LNS architectures for addition, subtraction, and multi-operand operations have been proposed in the literature using interpolation, linear, or polynomial approximation aiming at reducing the memory requirements, particularly for larger word lengths [27,28]. Furthermore mathematical decompositions and transformations of the basic operations, exploiting the particular characteristics of the functions, have been used to further simplify approximation [12,[27][28][29][30][31].…”

Section: A Design Methodology For Lns Systemsmentioning

confidence: 99%

“…In this context and to address the complicated required conversion to LNS, Muscedere et al have studied techniques for the conversion of binary to a multidigit-multidimensional logarithmic number system by using look-up tables [11]. Ismail and Coleman have presented a co-transformation procedure and an improved interpolation method that reduce the size of look-up tables facilitating their easy synthesis in logic [12]. Fu et al deal with LNS arithmetic optimizations on FPGAs [13].…”

Section: Literature Reviewmentioning

confidence: 98%

See 1 more Smart Citation

Logarithmic Number System and Its Application in FIR Filter Design

Paliouras

2017

Embedded Systems Design With Special Arithmetic and Number Systems

View full text Add to dashboard Cite

Data representation is an important parameter in the design of digital signal processors as it affects their performance and hardware complexity. Data representation influences the choice of algorithms and the hardware architecture, thus it has an impact on data storage requirements, processing performance, complexity, and power dissipation [1][2][3].The Logarithmic Number System (LNS) can be used to efficiently represent data in special-purpose processors. The efficiency of LNS stems from the properties of the logarithm exploited to reduce the basic arithmetic operations of multiplication, division, square roots, and squares to simple binary addition, subtraction, and right and left shifts, respectively [4]. Similarly, the computation of general roots and powers as well as of reciprocals are substantially simplified.Building on the reduced complexity of certain arithmetic operations, digital signal processor implementations can benefit from substantial architectural-level simplifications. Furthermore, beyond operation strength reduction, superior LNS dynamic range and numerical behavior, compared to conventional representations, are additional reasons that make LNS attractive. In order to fully utilize LNS potential, procedures are required to optimally define LNS design parameters and derive LNS solutions, matched to application specifications and requirements.

show abstract

Section: A Design Methodology For Lns Systemsmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 98%

Logarithmic Number System and Its Application in FIR Filter Design

Paliouras

2017

Embedded Systems Design With Special Arithmetic and Number Systems

View full text Add to dashboard Cite

show abstract

“…It is now 1.3 times that of the remainder of the subtraction curve ('Sub (lo)'), and accounts for 36% of the total storage. A die plot of the ELM was shown in [21]. There are two adder / subtractor units, known as 'multi-cycle ALUs'.…”

Section: B Lns Implementation Methodsmentioning

confidence: 99%

LNS with Co-Transformation Competes with Floating-Point

Coleman

Ismail

2016

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

The logarithmic number system has been proposed as an alternative to floating-point arithmetic. Multiplication, division and square-root operations are accomplished with inexpensive fixed-point methods, but addition and subtraction are considerably more challenging. Recent work has demonstrated that these operations too can be done with similar speed and accuracy to their FP equivalents, but the necessary circuitry is complex. In particular, it is dominated by the need for large ROM tables for the storage and interpolation of non-linear functions. We describe a new co-transformation procedure that eliminates much of the ROM space and allows the easy synthesis of the remainder in logic, and we then evaluate several interpolation methods that might benefit from it. Synthesised 32-bit implementations are compared with floating-point units, and show substantial reductions in delay, with equivalent accuracy and area.

show abstract

“…LNS multiplication process was divided into two categories, (1) lookup tables and interpolations based [7][8] and (2) Mitchell's algorithm based [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. Lookup tables and interpolation has required Read Only Memory (ROM).…”

Section: Literature Reviewmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

View full text Add to dashboard Cite

Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell's algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.

show abstract

ROM-less LNS

Cited by 26 publications

References 12 publications

Logarithmic Number System and Its Application in FIR Filter Design

Logarithmic Number System and Its Application in FIR Filter Design

LNS with Co-Transformation Competes with Floating-Point

An efficient architecture of iterative logarithm multiplier

Contact Info

Product

Resources

About