RTSAT: A Hybrid Satisfiability Solver for RTL Circuits

Abstract

This paper presents an efficient strategy to solve the satisfiability (SAT) problem for RTL designs. Boolean DPLL algorithm is extended into a unified procedure to solve the hybrid constraints combining the Boolean logic and arithmetic operations, and an efficient modeling method of RTL circuits is adopted. Powerful constraint propagation in both domains and efficient learning on the interface and arithmetic part are applied. The main contributions of this paper are the integration of constraint propagations in both domains and the propagating methods in word-level part using arithmetic operations. The experimental results demonstrate the efficiency of our approach.