Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and Beyond

Motoyama, K.; Straten, O. van der; Maniscalco, J.; Huang, Huai; Kim, Yb.; Choi, Jihwan P.; Lee, Jh.; Hu, C.‐K.; McLaughlin, P.; Standaert, T.; Quon, R.; Bonilla, G.

doi:10.1109/iitc.2018.8430296

Cited by 8 publications

(6 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, TaN thermally deposited using ALD has a higher number of impurities than PVD-fabricated TaN films, a lower film density, a higher resistance, and a lower interface quality, meaning that it cannot emulate the performance of PVD TaN at the same thickness. For this reason, PVD Ta and ALD TaN have been employed as bilayers (1 nm/1 nm) to reduce the thickness while ensuring the barrier properties [46]. Another approach is treating ALD-fabricated TaN in a PVD chamber to transform it into PVD-like film with optimal density and resistivity [47,48].…”

Section: Tan Barrier/liner Scalingmentioning

confidence: 99%

“…If the thickness is less than a certain threshold, it no longer functions as a Cu diffusion barrier. Based on past experimental results, it is unclear whether the barrier/liner combination can have a thickness lower than 2 nm [45][46][47]75]. However, a barrierless solution is required when the half pitch falls below 10 nm, and thus, new metals to replace Cu have been sought.…”

Section: Alternative Metalsmentioning

confidence: 99%

See 1 more Smart Citation

Recent Trends in Copper Metallization

Kim

2022

Electronics

View full text Add to dashboard Cite

The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO2 interconnects, but now that the technology generation has reached 1× nm or lower, a number of limitations have become apparent. Due to the integration limit of low-k materials, the increase in the RC delay due to scaling can only be suppressed through metallization. As a result, various metallization methods have been proposed, including traditional barrier/liner thickness scaling, and new materials and integration schemes have been developed. This paper introduces these methods and summarizes the recent trends in metallization. It also includes a brief introduction to the Cu damascene process, an explanation of why the low-k approach faces limitations, and a discussion of the measures of reliability (electromigration and time-dependent dielectric breakdown) that are essential for all validation schemes.

show abstract

Section: Tan Barrier/liner Scalingmentioning

confidence: 99%

Section: Alternative Metalsmentioning

confidence: 99%

Recent Trends in Copper Metallization

Kim

2022

Electronics

View full text Add to dashboard Cite

show abstract

“…Moreover, its higher melting point than Cu is expected to improve electro-migration performance. Furthermore, Ru is already used in industry-like Cu-based BEOL interconnects as a liner material [82]. Although it is not a focus of this review article, Ru-based BEOL processes (e.g., deposition, CMP, and etching) could therefore rapidly mature.…”

Section: Ru Interconnectmentioning

confidence: 99%

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

et al. 2022

View full text Add to dashboard Cite

The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.

show abstract

“…The combined PVD/ALD process with 10Å Co enables a 14% reduction in RC delay relative to control split (20Å PVD TaN + 30Å CVD Co). Motoyama et al [ 257 ] reported sidewall voids observed in case of Co liner, whereas void-free Cu fill was achieved with Ru liner in 30 nm pitch interconnects. The results indicate that Ru liner is superior to Co liner in terms of Cu fill at these nanoscale dimensions.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

View full text Add to dashboard Cite

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

show abstract

Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and Beyond

Cited by 8 publications

References 0 publications

Recent Trends in Copper Metallization

Recent Trends in Copper Metallization

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

State of the Art and Future Perspectives in Advanced CMOS Technology

Contact Info

Product

Resources

About