Run-time Mapping of Spiking Neural Networks to Neuromorphic Hardware

Balaji, Adarsha; Marty, Thibaut; Das, Anup; Catthoor, Francky

doi:10.1007/s11265-020-01573-8

Cited by 31 publications

(22 citation statements)

References 55 publications

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“…DecomposeSNN [16] decomposes an SNN to improve the cluster utilization. There are also performance-oriented SNN mapping approaches such as [7,11,15,86], energy-aware SNN mapping approaches such as [101], circuit aging-aware SNN mapping approaches such as [10,67,84,88,91], endurance-aware SNN mapping approaches such as [93,99,102], and thermal-aware SNN mapping approaches such as [100]. These approaches are evaluated with emerging SNN based applications [9,31,43,50,64,75], which we also use to evaluate DFSynthesizer.…”

Section: Related Workmentioning

confidence: 99%

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Song¹,

Chong²,

Balaji³

et al. 2021

Preprint

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Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tilebased neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine-learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine-learning programs. Our results demonstrate that DFSynthesizer provides much tighter performance guarantee compared to current mapping approaches. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

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Section: Related Workmentioning

confidence: 99%

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Song¹,

Chong²,

Balaji³

et al. 2021

Preprint

Self Cite

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“…Therefore, systemsoftware frameworks such as NEUTRAMS [58], NeuroXplorer [59], Corelet [60], PACMAN [61], and LAVA [62] consist of 1) a compiler, which partitions an SNN model into clusters such that the neurons and synapses of each cluster can be mapped to a crossbar of the hardware, and 2) a run-time manager, which maps the clusters of an SNN to the cores of a many-core hardware. To this end, several mapping strategies have been proposed, including optimizing for energy [63]- [66], throughput [67]- [70], resource utilization [56], [58], [62], [71], [72], circuit aging [30]- [34], inference lifetime [39], and write endurance [35]- [37]. These mapping techniques all use some variant of the SNN-partitioning approach proposed in SpiNeMap [64].…”

Section: Snnsmentioning

confidence: 99%

Design Technology Co-Optimization for Neuromorphic Computing

Paul¹,

Song²,

Das³

2021

Preprint

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We present a design-technology tradeoff analysis in implementing machine-learning inference on the processing cores of a Non-Volatile Memory (NVM)-based many-core neuromorphic hardware. Through detailed circuit-level simulations for scaled process technology nodes, we show the negative impact of design scaling on read endurance of NVMs, which directly impacts their inference lifetime. At a finer granularity, the inference lifetime of a core depends on 1) the resistance state of synaptic weights programmed on the core (design) and 2) the voltage variation inside the core that is introduced by the parasitic components on current paths (technology). We show that such design and technology characteristics can be incorporated in a design flow to significantly improve the inference lifetime. 1 NVMs are also used in classical von Neumann computing to mitigate the performance and energy bottlenect of DRAM [19]-[25].

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“…Therefore, system software frameworks such as NEUTRAMS [20], NeuroXplorer [21], Corelet [22], and PACMAN [23] consist of 1) a compiler, which partitions a SNN model into clusters such that the neurons and synapses of each cluster can be mapped to a crossbar of the hardware, and 2) a run-time manager, which maps the clusters of an SNN to the cores of a many-core hardware. To this end, several mapping strategies are proposed, including optimizing for energy [7], [24]- [26], throughput [27]- [30], resource utilization [20], [31]- [33], circuit aging [34]- [38], inference lifetime [39], and endurance [40]- [42]. All these mapping techniques use some variants of the SNN partitioning approach proposed in SpiNeMap [24].…”

Section: Background and Related Workmentioning

confidence: 99%

A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware

Song¹,

Varshika²,

Das³

et al. 2021

Preprint

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The design of many-core neuromorphic hardware is getting more and more complex as these systems are expected to execute large machine learning models. To deal with the design complexity, a predictable design flow is needed to guarantee realtime performance such as latency and throughput without significantly increasing the buffer requirement of computing cores. Synchronous Data Flow Graphs (SDFGs) are used for predictable mapping of streaming applications to multiprocessor systems. We propose an SDFG-based design flow for mapping spiking neural networks (SNNs) to many-core neuromorphic hardware with the objective of exploring the tradeoff between throughput and buffer size. The proposed design flow integrates an iterative partitioning approach, based on Kernighan-Lin graph partitioning heuristic, creating SNN clusters such that each cluster can be mapped to a core of the hardware. The partitioning approach minimizes the inter-cluster spike communication, which improves latency on the shared interconnect of the hardware. Next, the design flow maps clusters to cores using an instance of the Particle Swarm Optimization (PSO), an evolutionary algorithm, exploring the design space of throughput and buffer size. Pareto optimal mappings are retained from the design flow, allowing system designers to select a Pareto mapping that satisfies throughput and buffer size requirements of the design. We evaluated the design flow using five large-scale convolutional neural network (CNN) models. Results demonstrate 63% higher maximum throughput and 10% lower buffer size requirement compared to state-of-theart dataflow-based mapping solutions.

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Run-time Mapping of Spiking Neural Networks to Neuromorphic Hardware

Cited by 31 publications

References 55 publications

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Design Technology Co-Optimization for Neuromorphic Computing

A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware

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