SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Abstract

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

A Review of Recent Techniques in Mixed-Criticality Systems

“…Despite intensive studies on energy e±ciency, these power-saving methods have not been applied in safety-critical areas. Lenz et al 39 studied an architecture's requirements for a low-power MC system such as the fault tolerance and safety arguments, the power and energy e±ciency, predictability and real-time features. Based on this, they introduced European project SAFE-POWER used to solve the problem of power management in MC systems real-time response, predictability, as well as power and energy e±ciency requirements.…”