Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converter

Xiang, Jin; Cheng, Jun; Li, Liang; Zhang, Ting; Gong, Liao; Ma, Qiyun

doi:10.1109/asicon.2015.7516939

2015 IEEE 11th International Conference on ASIC (ASICON) 2015

DOI: 10.1109/asicon.2015.7516939

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Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converter

Jin Xiang

Jun Cheng

Liang Li³

et al.

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Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converter

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