SAPTM: Towards High-Throughput Per-Flow Traffic Measurement with a Systolic Array-Like Architecture on FPGA

Abstract

Per-flow traffic measurement has emerged as a critical but challenging task in data centers in recent years in the face of massive network traffic. Many approximate methods have been proposed to resolve the existing resource-accuracy trade-off in per-flow traffic measurement, one of which is the sketch-based method. However, sketches are affected by their high computational cost and low throughput; moreover, their measurement accuracy is hard to guarantee under the conditions of changing network bandwidth or flow size distribution. Recently, FPGAplatforms have been widely deployed in data centers, as they demonstrate a good fit for high-speed network processing. In this work, we aim to address the problem of per-flow traffic measurement from a hardware architecture perspective. We thus design SAPTM, a pipelined systolic array-like architecture for high-throughput per-flow traffic measurement on FPGA. We adopt memory-friendly D-left hashing in the design of SAPTM, which guarantees high space utilization during flow insertion and eviction, successfully addressing the challenge of tracking a high-speed data stream under limited memory resources on FPGA. Evaluations on the Xilinx VCU118 platform with real-world benchmarks demonstrate that SAPTM possesses high space utilization. Comparisons with state-of-the-art sketch-based solutions show that SAPTM outperforms comparison methods in terms of throughput by a factor of 14.1x–70.5x without any accuracy loss.

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

“…Blockλ and Blockδ execute the same functions as these blocks in FSM U 3 . The Blockλ generates functions (12), the Blockδ the functions (16). If R Q ≤ S L , then Blockλ includes only a single level of LUTs.…”

“…Each row of this table corresponds to a pair < Y q , I np > determining the state a s ∈ A. The terms of SOPs (16) are conjunctions of variables z r ∈ Z and v r ∈ V. The corresponding literals are determined by codes K(Y q ) and K(I np ).…”

“…Thus, an FSM based on this principle implements systems (12), (13), (16) and (17). It is an FSM U 3 shown in Figure 4.…”

“…It is an FSM U 3 shown in Figure 4. In FSM U 3 , the BlockZV implements systems (13) and (17); the Blockδ implements input memory functions represented as (16); the Blockλ implements the system (12). Thus, there are only two levels of logic between inputs and outputs in the case of FSM U 3 .…”

“…In this article we consider methods of implementing FSM circuits in the context of field programmable gate arrays [11][12][13]. These chips are very popular devices used for implementations of digital systems [2,[14][15][16][17][18]. This fact explains our choice of FPGA-based Mealy FSMs as a research object.…”