Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs

Abstract

Latch-based designs have many benefits over their flip-flop based counterparts but have limited use partially because most RTL specifications are flop-centric and automatic conversion of FF to latch-based designs is challenging. Conventional conversion algorithms target master-slave latchbased designs with two non-overlapping clocks. This paper presents a novel automated design flow that converts flipflop to 3-phase latch-based designs. The resulting circuits have the same performance as the master-slave based designs but require significantly less latches. Our experimental results demonstrate the potential for savings in the number of latches (21.3%), area (5.8%), and power (16.3%) on a variety of ISCAS, CEP, and CPU benchmark circuits, compared to the master-slave conversions. * This work was partially supported by NSF Grant #1619415 and DARPA Contract #HR001119C0070. P. A. Beerel also consults for Galois, Inc. in the area of asynchronous design. c denote the cycle time of the two-phase non-overlapping clocks and assuming E12 = E21 = Tc, Equation 1 implies e2 − e1 = T 2P c + e1 − e2 = Tc and thus, T 2P c = 2Tc. In other words, the frequency of the two-phase clocks must be half that of the original FF-based design.