Scalable Adaptive Scan (SAS)

Chandra, Anshuman; Kapur, R.; Kanzawa, Y.

doi:10.1109/date.2009.5090896

Cited by 35 publications

(22 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The technique presented in [16] also eliminated the need for large number of multiplexors needed for scan chain reconfiguration and therefore reduced routing congestion as well. Though the work presented in [16] used simple shift register to implement a compression solution, it was preliminary and incomplete work. It only addressed the input side compression problem with no discussion on practical DFT and manufacturing test issues like diagnostics, congestion and timing issues.…”

Section: Zscan Compressed Dft Insertionmentioning

confidence: 96%

“…In [20] it was shown how simple scan chain reconfiguration can break the input cell dependencies present in ILS and was shown to achieve high test data compression using a single scan input. An improvement over [20] was presented in [16] where it was shown that compression efficiency could be greatly improved by using simple shift registers. The technique presented in [16] also eliminated the need for large number of multiplexors needed for scan chain reconfiguration and therefore reduced routing congestion as well.…”

Section: Zscan Compressed Dft Insertionmentioning

confidence: 97%

“…An improvement over [20] was presented in [16] where it was shown that compression efficiency could be greatly improved by using simple shift registers. The technique presented in [16] also eliminated the need for large number of multiplexors needed for scan chain reconfiguration and therefore reduced routing congestion as well. Though the work presented in [16] used simple shift register to implement a compression solution, it was preliminary and incomplete work.…”

Section: Zscan Compressed Dft Insertionmentioning

confidence: 97%

“…Compression solutions using reconfiguration and shift registers have been studied in the past in [20] and [16]. In [20] it was shown how simple scan chain reconfiguration can break the input cell dependencies present in ILS and was shown to achieve high test data compression using a single scan input.…”

Section: Zscan Compressed Dft Insertionmentioning

confidence: 99%

“…In [16] unification of scan compression and TAMs has been analyzed to deliver a low-pin count hierarchical testing methodology that delivers high compression quality of results (QoR). The paper shows how active TAMs can be designed by using simple shift registers that enable running pattern generation at the top level while allowing DFT insertion at the block level in a hierarchical test flow.…”

mentioning

confidence: 99%

See 4 more Smart Citations

A Case Study on Implementing Compressed DFT Architecture

Chandra

Chebiyam

Kapur

2014

2014 IEEE 23rd Asian Test Symposium

Self Cite

View full text Add to dashboard Cite

Scan Compression has become the default design-for-test (DFT) methodology for achieving high quality test at lower costs. Just as scan matured over a span of 40 years we are now observing Scan Compression improving and adapting to the needs of current designs. In this paper we present an industrial case study demonstrating how the DFT flows are impacted in the presence of compression logic for test. We develop various DFT architectures using the zScan compression technology and discuss the pros and cons of each flow w.r.t. pin limited test and modular DFT insertion. We also show that the decisions of pin count and scan chain count dramatically impact the final QoR i.e., test application time and test data volume required to test the chip.

show abstract

Section: Zscan Compressed Dft Insertionmentioning

confidence: 96%