Scaling guidelines for CMOS linear analog design

Abstract

This paper proposes scaling guidelines for CMOS analog design during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. The proposed guidelines are applied to linear examples: OTAs. The results are compared on four CMOS processes whose minimum length are 0.8 μ μ μ μm, 0.35 μ μ μ μm, 0.25 μ μ μ μm and 0.12 μ μ μ μm.