Scaling reconfigurable emulation of quantum algorithms at high precision and high throughput

Abstract

Summary The general approach for emulating quantum algorithms on classical platforms has been through representing them as gate‐based quantum circuits. However, direct implementation of quantum circuits significantly increases the hardware resource utilization and system latency of classical emulators. In this paper, we investigate multiple implementation models alternative to conventional emulation approaches, as feasible solutions to the scalability problem in classical emulation of quantum circuits. In the first model, the quantum circuit functionality is reduced to equivalent, arithmetic (multiply‐and‐accumulate) operations and combined with two computation methods, based on lookup and dynamic generation. In the second model, a kernel operation is extracted from the quantum circuit based on its functionality, and the kernel is iterated through all input quantum states. The proposed emulation models provide space and time optimizations, significantly reducing resource utilizations and latencies and improving scalability. We use these models to develop a highly scalable hardware emulator that is based on reconfigurable technology for efficient simulations of full quantum algorithms and circuits. Our hardware implementations support single precision floating point arithmetic for improved accuracy, and contain fully pipelined designs for high throughput. We investigate quantum algorithms such as quantum Fourier transform and quantum wavelet transform and explore different hardware architectures and optimizations. Experimental results and analysis are provided for the architectures in terms of resource consumption and emulation time. The experiments are carried out on a high‐performance reconfigurable computing system and the obtained results show that the proposed emulator is feasible for running and testing a variety of quantum algorithms.

Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

“…In this section, we elaborate our methodology that uses QHT to achieve dimension reduction. We also detail the corresponding emulation hardware architectures that were implemented [41].…”

“…Our proposed methodology for dimension reduction using quantum wavelet transforms is shown in Figure 2 [41]. In our proposed approach, each pixel of the input image is encoded as a basis coefficient of a quantum state.…”

Quantum annealing distributed integer decomposition study of local field coefficient <italic>h</italic> and coupling coefficient <italic>J</italic> with stability Ising model

“…业内长期以来认为Shor算法是唯一有效的攻击 RSA的量子计算算法, 且在抗量子密码的研究方面几 乎仅考虑到Shor算法的潜在威胁. 至今已有很多研究 者尝试各种量子系统来实现Shor算法 [1][2][3][4] . 目前分解n 位大数需要2n+1到3n+0.002nlgn逻辑量子比特(Qubits) [5,6] , 由于受限于量子比特数与精度, 目前Shor算法 最大可实现整数85的分解 [7] .…”

A novel approach for emulating quantum computers on classical platforms

“…Mahmud et al proposed multiple alternative models as feasible solutions to the scalability problem of emulating quantum circuits using the classical resources, and they further used these models to develop a highly scalable hardware emulator that is based on reconfigurable technology, which can efficiently simulate full quantum algorithms and circuits with improved and lower resource utilization and circuit latencies. Their hardware emulators can support single floating‐point precision for high precision and contain a fully pipelined architecture for high throughput.…”