Scheduling tests for VLSI systems under power constraints

Abstract

Abstract-This paper considers the problem of testing VLSI integrated circuits in minimum time without exceeding their power ratings during test. We use a resource graph formulation for the test problem. The solution requires finding a power-constrained schedule of tests. Two formulations of this problem are given as follows: 1) scheduling equal length tests with power constraints and 2) scheduling unequal length tests with power constraints. Optimum solutions are obtained for both formulations. Algorithms consist of four basic steps. First, a test compatibility graph is constructed from the resource graph. Second, the test compatibility graph is used to identify a complete set of time compatible tests with power dissipation information associated with each test. Third, from the set of compatible tests, lists of power compatible tests are extracted. And finally, minimum cover table approach is used to find an optimum schedule of power compatible tests.

A reconfigurable power-conscious core wrapper and its application to soc test scheduling

“…Several test scheduling techniques have been proposed [1,4,6,7,8,9,11,12,13,14,15,16,17,18]. Chou et al proposed a technique for general systems where each test has a fixed test time and a fixed power consumption value [4].…”

“…Chou et al proposed a technique for general systems where each test has a fixed test time and a fixed power consumption value [4]. The objective is to organize the tests in such a way that the total test application time is minimized while test conflicts and test power limitation are taken in to account [4].…”

“…Test conflicts can be modelled using a resource graph [4]. The system in Figure 1 is modelled as a resource graph as in Figure 14, where the nodes represents the tests and the resources.…”

“…Chou et al introduced a power model where each test is denoted with a fixed power consumption value [4].…”

“…• design for low power testing where the system is designed to minimize test power consumption, which allows consequently testing at a higher clock frequency [5,21,22,24], and • test scheduling where the tests are organized in such a way that the test time is minimized while considering test power limitations and test conflicts [1,4,6,7,8,9,11,12,13,14,15,16,17,18].…”