SEA: fast power estimation for micro-architectures

Kalla, Praveen; Henkel, Joerg; Hu, Xiaobo Sharon

doi:10.1109/icasic.2003.1277429

Cited by 2 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This approach does not address the application specific power consumption estimation. Estimating power consumption due to software execution has been well studied [5,6,7,8]. There is limited amount work in the area of power aware video playback and the existing work primarily deals with system level adaptation such as frequency scaling [9,10].…”

Section: Introductionmentioning

confidence: 99%

Resource estimation methodology for multimedia applications

et al. 2007

View full text Add to dashboard Cite

Reducing the product development cycle time is one of the most important and challenging problems faced by the industry today. As the functionality and complexity of devices increases, so does the time required to design, test, and develop the devices. Developing products rapidly in the face of this increasing complexity requires new methodologies and tools. This paper presents a methodology for estimating the resources consumed by a video decoder. The proposed methodology enables resource estimation based on high level user requirements. Component architecture for a H.264 video decoder is developed to enable design space exploration. The resources required to decode H.264 video are estimated based on a measure of the complexity of the H.264 bitstreams and the target architecture. The proposed approach is based on the hypothesis that the complexity of a H.264 video bitstream significantly influences resource consumption and the complexity of a bitstream can thus be used to determine resource estimation. The bitstream complexity is characterized to capture the data dependencies using a process called Bitstream Abstraction. The decoder is componentized and component level resource requirements determined in a process called Decoder Abstraction. The proposed methodology uses Bitstream Abstraction together with Decoder Abstraction to estimate resource requirements. A component model for the H.264 video decoder is developed. Resources consumed by each component are determined using the VTune performance analyzer. These resource estimates and video bitstream complexity are used in developing a parametric model for resource estimation based on bitstream complexity. The proposed methodology enables high level resource estimation for multimedia applications without a need for extensive and time consuming simulations.

show abstract

Section: Introductionmentioning

confidence: 99%

Resource estimation methodology for multimedia applications

et al. 2007

View full text Add to dashboard Cite

show abstract

“…Power estimation tools working at the instruction level have been extensively proposed. Some of them achieve high accuracy in terms of energy estimation in a short simulation time; however, these approaches need of a deep processor characterization and their power results show big deviations with respect to the original behavior [KHH03]. Compiler [KKV"'"02] and source code [SJM02] estimation tools have also been proposed, which partially could solve the target dependence problem.…”

Section: Chapter2 Relatedworkmentioning

confidence: 99%

Power estimation and power optimization policies for processor-based systems

Rodrigo¹

View full text Add to dashboard Cite

This PhD Thesis proposes new and effective approaches to reduce and estímate the power consumption in processor-based architectures. This work targets embedded systems, inorder and out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designad to reduce or estimate the power consumption while keeping the performance constraints of the application and allowing the porting to other processor architectures without a hard effort by the designen In this context, a first work was the design of a cache power estimation tool (called IN^ CAPE), which works in parallel with the processor simulator. The power estimation utihty bases its results on an analytical power model, which has been fed with the expHcit calculation of the statistical switching activity.After that, reducing the power consumption in the register file of the processor architecture was the goal of the research. Given that the register file is one of the most power-hungry devices, firstly an efficient hardware mechanism to tum the unused registers of the register file into a low power state has been described. A DVS technique is used to keep the Information stored in the registers while reducing the power consumption to a mínimum. This hardware technique has been compared to an approach based on a power-aware compiler, which modifies the register assignment to improve the results obtained with the banking of the register file, as well as to reduce the number of required ports.Out-of-order architectures have also been addressed, with a higher degree of complexity. For these systems, compiler and hardware approaches have also been proposed to efficiently reduce the power consumption of the register file.Finally, MPSoCs are also the new paradigm of high-performance microprocessor design, where the power dissipation becomes an even more dramatic problem. These architectures present complex design issues where the power-performance trade-off has to be carefully analyzed in order to bring efficient designs. The work presented in this Ph. D. aims at overcoming the limitation of theoretical and highly abstract models, unable to target the desired functional simulation and power estimation. This work also presents interesting results in terms of dynamic power management, voltage/frequency scaling and design space exploration in MPSoCs.

show abstract

SEA: fast power estimation for micro-architectures

Cited by 2 publications

References 9 publications

Resource estimation methodology for multimedia applications

Resource estimation methodology for multimedia applications

Power estimation and power optimization policies for processor-based systems

Contact Info

Product

Resources

About