Security of Emerging Memory Chips

Ferdaus, Farah; Rahman, Tauhidur

doi:10.1007/978-3-030-64448-2_14

Cited by 6 publications

(2 citation statements)

References 51 publications

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“…The temporal and geographical position of reference is explored. The objective is to examine the evolution of creative, associative mapping throughout time [10]. Physical memory is known as associative memory.…”

Section: A Security Issues In Cache Memorymentioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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This paper provides an overview of blockchain technology's security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip's memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R=42.3 and R=42.3K ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes 11.65µW of power and has 33 transistors which are lowest from other architectures.INDEX TERMS Circuit of write driver (CWD), sense amplifier (SA), current differential sense amplifier (CDSA), charge transfer differential sense amplifier (CTDSA), voltage latch sense amplifier (VLSA), six transistor static random-access memory (6T-SRAM).

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Section: A Security Issues In Cache Memorymentioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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“…Random thermal fluctuations and process variation exacerbate the intrinsic stochasticity of the magnetic orientation switching of MRAM cells; hence, significantly varies the switching time of the cell over the entire memory array. Therefore, the MRAM write failure rate increase significantly as temperature increases [38]. To incorporate the temperature effect, hence, covering maximum erroneous addresses, we can perform the characterization at a high temperature compared with the operating temperature used during normal execution.…”

Section: Effect Of Environmental and Chip Variationsmentioning

confidence: 99%

Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

Ferdaus,

Talukder,

Rahman

2021

Preprint

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Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results and error-resilient image application reveal that the proposed AC framework provides a significant performance improvement and demonstrates a maximum reduction in MRAM write current of ∼66% on average with negligible or no loss in output quality.

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BTI aging-based physical cloning attack on SRAM PUF and the countermeasure

Duan

Sai

2023

Analog Integr Circ Sig Process

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Security of Emerging Memory Chips

Cited by 6 publications

References 51 publications

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

BTI aging-based physical cloning attack on SRAM PUF and the countermeasure

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