SHE PWM based 21 level inverters with hardware analysis

Abstract

Recently, the advancement of multilevel inverters (MLI) has been a crucial factor in high power and medium voltage applications. This MLI has multiple topologies and has been used in a variety of applications. Cascaded MLI is preferred over other forms of multilevel inverter topologies. Nonetheless, significant obstacles are encountered when implementing these topologies. They necessitate an increased number of switches, DC sources, capacitors, and diodes. Increased losses and total harmonic distortion (THD) will be present in the system. In addition, the MLI is more expensive. The better construction of a multilevel inverter results in more output levels with fewer switches, sources, and driver circuits, as well as low THD. A new single-phase cascaded asymmetrical DC voltage sources based multilevel inverter design and the selective harmonic elimination (SHE) approach are used to attain these goals. After confirming in MATLAB/Simulink, the hardware implementation of the multilevel inverter in 21 levels was completed in this article.