SHUM-uCOS: A RTOS using multi-task model to reduce migration cost between SW/HW tasks

Weinan

7th IEEE International Conference on Computer and Information Technology (CIT 2007)

et al. 2007

Multimedia processor designers are always challenged by performance, cost and flexibility. Due to the technological advance in FPGA, one of the promising solutions is to enable dynamically reconfigurable SoC in multimedia application. This paper utilizes Reconfigurable SoC (RSoC) in multimedia processing. We propose a feasible run-time reconfigurable system where dynamically Reconfigurable Processing Unit (RPU) is integrated with General Purpose Processor (GPP) at different abstraction level. Furthermore, a simple analysis on performance improvement is given accordingly. As a proof-of-concept, an RSoC prototype based on Xilinx Virtex-II Pro FPGA is also presented at last.

Section: Operating System Abstraction Levelmentioning

confidence: 99%

Enabling Reconfigurable SoC in Multimedia Processing

Weinan

7th IEEE International Conference on Computer and Information Technology (CIT 2007)

et al. 2007

“…The Unified Software/Hardware multithread programming Model supporting Dynamic Reconfiguration (SHUMDR) we proposed aims at hiding the implementation details of the hardware task and offering a unified hardware/software thread view [8]. Figure 1 depicts the layered structure of SHUMDR, which consists of four abstraction levels, hardware platform on DRSoC, HTI design and adaptation, extended OS kernel and Pthreads compatible SHUMDR, from low to high respectively.…”

Section: Unified Multithread Programming Model On Drsocmentioning

confidence: 99%

“…Making use of our previous works on OS kernel extension and hardware tasks scheduling [8] [9]. In this paper, we adopt unified hardware/software multithread programming model as our solution for hybrid hardware/software task design.…”

Section: Introductionmentioning

confidence: 99%

The Hardware Thread Interface Design and Adaptation on Dynamically Reconfigurable SoC

Weinan

2009 International Conference on Embedded Software and Systems

et al. 2009

Nowadays, one of the challenges for creating a mixed hardware/software application on dynamically reconfigurable SoC is how to provide a unified programming model for hybrid hardware/software tasks and a portable interface adaptation for dynamically reconfigurable hardware tasks. In this paper, a POSIX-compliant hardware thread interface is proposed for data stream driven applications, serving for unified hardware/software multithread programming. At the same time, the stub/interface adaptation mechanism is also presented to support shared buffer based inter-thread communication/synchronization. At last, the experimental results on AES encryption/decryption hardware thread show that the interface design and adaptation could exploit programming transparency while effectively keep hardware efficiency.

2014 Brazilian Symposium on Computing Systems Engineering

“…The well known concept of software thread, similar as the POSIX model [3], can be applied and shift the paradigm HW thread, providing a unified transparent model [3]. The coexistence of a hybrid, software and hardware model in an operating system environment, raises concerns namely regarding an unified programming model, portability, legacy software support, suitable interface and synchronization mechanisms, communication overhead and resource optimization [4], [5], [6], eventually exacerbated in resource constrained embedded contexts. As an example of an unified hardware/software thread programming model, [4], [5], show some of the benefis of this methodology.…”

Section: Related Workmentioning

confidence: 99%

“…The coexistence of a hybrid, software and hardware model in an operating system environment, raises concerns namely regarding an unified programming model, portability, legacy software support, suitable interface and synchronization mechanisms, communication overhead and resource optimization [4], [5], [6], eventually exacerbated in resource constrained embedded contexts. As an example of an unified hardware/software thread programming model, [4], [5], show some of the benefis of this methodology. Communication overhead on a shared bus, and resource utilization are maintained low in both cases, while still offering performance improvements.…”

Section: Related Workmentioning

confidence: 99%

Co-Designed FreeRTOS Deployed on FPGA

Pereira

Oliveira

Pinto

et al. 2014

Most embedded systems are bound to real-time constraints. Two of the critical metrics presented in these systems are determinism and latency. Due to growing in complexity of embedded applications, real time operating systems (RTOS) are needed, not only to hide the increasingly complex hardware, but also to provide services to the system's running tasks. Unfortunately, this new layer on an embedded system puts more pressure on the aforementioned metrics. One of the ways to cope with this problem is to offload RTOS run-time services to the hardware layer.This paper presents a hybrid hardware/software implementation of this technique upon the well known FreeRTOS, improving system's latency and predictability, by migrating critical runtime services to hardware. The developed hardware accelerators were synthesized on a field-programmable gate array (FPGA), exploiting the point-to-point bus Fast Simplex Link (FSL) to interconnect to the Xilinx's Microbaze soft-core processor.