Signal generators for cost effective BIST of ADCs

Vasan, Bharath K; Duan, Jing; Zhao, Chen; Geiger, R.L.; Chen, Degang J.

doi:10.1109/ecctd.2009.5274967

Cited by 14 publications

(9 citation statements)

References 6 publications

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“…More recent advancements in ADC testing algorithms have introduced BIST systems that operate using Stimulus Error Identification and Removal (SEIR) based linearity testing in order to estimate INL [6], [7]. The algorithm ensures the uncertainty in INL is bounded by a known value but increases the memory and ALU requirements significantly.…”

Section: Integral Non-linearity (Inl)mentioning

confidence: 99%

“…Whether it would be necessary to integrate SEIR testing into OBIST at the cost of significantly more hardware overhead is still uncertain until more empirical data on the error bound for the INL estimates in OBIST is obtained. At the very least, it offers a feasible alternative to estimate INL if (6) does not produce sufficiently accurate results.…”

Section: Integral Non-linearity (Inl)mentioning

confidence: 99%

See 1 more Smart Citation

Oscillation Built-In-Self-Test for ADC linearity testing in deep submicron CMOS technology

Chan¹,

Nordin²,

Chan³

et al. 2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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This paper proposes an Oscillation BIST (OBIST) that is meant to test ADCs fabricated in sub 100nm processes. The design is intended to be capable of testing a 10-bit ADC that was designed in 40nm CMOS. The design scheme presents a simple analog stimulus generator that was designed in 40nm CMOS together with schematic based simulation results. There is also a description of a calibration circuit and a highlevel implementation of a BIST control system to run the BIST and to calculate static parameters such as Differential Non-linearity (DNL) and Integral Non-linearity (INL). Simulation results for the analog stimulus generator suggest that OBIST might still be a viable method to test ADCs despite device scaling to sub 100nm processes.

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Section: Integral Non-linearity (Inl)mentioning

confidence: 99%

Section: Integral Non-linearity (Inl)mentioning

confidence: 99%

Oscillation Built-In-Self-Test for ADC linearity testing in deep submicron CMOS technology

Chan¹,

Nordin²,

Chan³

et al. 2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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“…The first problem can be avoided if two stimuli are used instead of a high quality stimulus [2]- [9]. In [10], it is proposed how these two stimuli can be generated using a simple CMOS circuit and few other proposals exist as well [11], [12]. Solutions for the second problem are proposed in [13], [14] but those are dedicated to linearity tests using one high-quality stimulus.…”

Section: Introductionmentioning

confidence: 97%

Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs

Korhonen

Kostamovaara

2011

2011 Sixteenth IEEE European Test Symposium

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This paper proposes how the static linearity test method for DAC-ADC pairs using two low-quality signals can be optimized in terms of the used memory resources. The test is split into small segments so that the full histograms can be replaced by small ones. In the case of 16-bit ADC, the histogram memory requirement of an unoptimized algorithm is 131072 bytes while the proposed optimization cuts it down to 96 bytes. Test accuracy remains unchanged and the only cost of the memory optimization is 10 % increase in test time. In addition, it is proposed how the calculation algorithm can be modified so that floating-point arithmetics can be replaced by fixed-point arithmetics. This decreases the time used to calculate the INL and DNL estimates for each code by a factor of ten. The proposed optimizations are targeted for the self-testing of devices including DAC, ADC and some (limited) calculation and memory resources, e.g. microcontrollers or system-on-chip devices.

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“…This type of stimulus, due to the shape of its spectrum should only be used in low frequency tests [16]. Recently, as happened with the sinusoidal signal, there are being proposed algorithms for BIST which use these stimuli with some amount of distortion and low linearity [17,18]. All these algorithms take the ADCs under test as a black box.…”

Section: Introductionmentioning

confidence: 99%

ADC built-in-self-test based on a pseudorandom uniform noise generator

Evans

2014

Design of Circuits and Integrated Systems

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This paper describes a digital built-in-self-test (BIST) solution to ADC dynamic performance testing. The proposed ADC BIST system is based in a uniform histogram approach to test the linearity of ADCs. A pipeline ADC with a resolution of 10 bits, a DAC with the same resolution as the ADC under test and the proposed BIST scheme were modeled and simulated in MATLAB to prove its validity. Several 32 bits pseudorandom uniform noise generators were evaluated. When compared with the Gaussian histogram approach, the obtained results show that the error on the maximum INL is 0.13 LSB for the Mersenne twister pseudorandom uniform noise generator and an adequate statistical significance is obtained with a quarter of the samples. Additionally, the number and complexity of the circuits are reduced.

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Signal generators for cost effective BIST of ADCs

Cited by 14 publications

References 6 publications

Oscillation Built-In-Self-Test for ADC linearity testing in deep submicron CMOS technology

Oscillation Built-In-Self-Test for ADC linearity testing in deep submicron CMOS technology

Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs

ADC built-in-self-test based on a pseudorandom uniform noise generator

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