SIKE Round 2 Speed Record on ARM Cortex-M4

Seo, Hwajeong; Jalali, Amir; Azarderakhsh, Reza

doi:10.1007/978-3-030-31578-8_3

Cited by 17 publications

(12 citation statements)

References 16 publications

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“…Code Size Scalability SIKE ECC RSA Speed Record Hybrid Protocol Multi-Precision Multiplication Groot † [9] 1284 Santis and Sigl † [10] 1264 Fujii and Aranha † [11] 622 Haase and Labrique [12] 452 Koppermann et al [13] -Seo et al [14] 452 (U) Seo et al (SIKE) [14] 3,396 (U) This work 260 (L,P) Multi-precision squaring Groot † [9] 1168 Santis and Sigl † [10] 882 Fujii and Aranha † [11] 562 Haase and Labrique [12] 324 Seo et al [14] 320 (U) Seo et al (SIKE) [14] 2372 (U) This work 324 (L,P) † symbol indicates implementations with fast reduction.…”

Section: Methodsmentioning

confidence: 99%

“…The proposed implementation obtained the smallest code size and reasonably fast execution timing. Previous work in CANS'19 [14] requires 44,688 bytes while the proposed implementation requires 28,816 bytes for SIKEp751, which is a code reduction of 35.5%. Furthermore, we first implemented the SIKEp610 protocol on 32-bit ARM Cortex-M4 microcontrollers.…”

Section: Comparison Of Cans'19mentioning

confidence: 99%

“…Previous work in CANS'19 [14] successfully evaluated the SIKE round 2 schemes on 32-bit ARM Cortex-M4 microcontrollers. In order to accelerate the execution timing, modular multiplication, and squaring operations are optimized for specific parameters of SIKEp434, SIKEp503, and SIKEp751.…”

Section: Comparison Of Cans'19mentioning

confidence: 99%

“…However, the implementation of SIDHp751 requires 18 s to exchange the keys. In [14], they implemented integer multiplication with operand caching (in UMAAL) and pipeline-friendly programming. The results show that SIKEp434 requires only 1.5 s.…”

Section: Introductionmentioning

confidence: 99%

“…In Table 1, both multi-precision multiplication implementation and multi-precision squaring implementation are compared. The fastest performance is achieved by [14]. For the 256-bit ECC implementation (e.g., NIST P-256 and Curve25519), 772 bytes are required for the multiplication and squaring implementations.…”

Section: Introductionmentioning

confidence: 99%

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Memory Efficient Implementation of Modular Multiplication for 32-bit ARM Cortex-M4

Seo

2020

Applied Sciences

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In this paper, we present scalable multi-precision multiplication implementation and scalable multi-precision squaring implementation for 32-bit ARM Cortex-M4 microcontrollers. For efficient computation and scalable functionality, we present optimized Multiplication and ACcumulation (MAC) techniques for the target microcontrollers. In particular, we present the 64-bit wise MAC operation with the Unsigned Long Multiply with Accumulate Accumulate (UMAAL) instruction. The MAC is used to perform column-wise multiplication/squaring (i.e., product-scanning) with general-purpose registers in an optimal way. Second, the squaring algorithm is further optimized through an efficient doubling routine together with an optimized product-scanning method. Finally, the proposed implementations achieved a very small memory footprint and high scalability to cover algorityms ranging from well-known public key cryptography (i.e., Rivest–Shamir–Adleman (RSA) and Elliptic Curve Cryptography (ECC)) to post-quantum cryptography (i.e., Supersingular Isogeny Key Encapsulation (SIKE)). All SIKE round 2 protocols were evaluated with the proposed modular reduction implementations. The results demonstrate that the scalable implementation can achieve the smallest code size together with a reasonable performance.

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