Simulation of multi-core power-network for early software development

Abstract

IBM server-systems are extremely complex, employing multiple processors, peripherals, interconnects, etc. Multiple voltage and power domains are also employed for power-efficient designs. Developing software for such an architecture, in absence of target platform, is an extremely error-prone affair. Bring-up of software once the hardware is available detects large amount of bugs, throwing the project cost and schedule out of control. This paper introduces a methodology to model the power-control network, incorporated within IBM system-level simulation environment. This methodology helps to debug, verify and fine tune the server software much before the availability of the target hardware. lJse of this methodology enables detecting the bugs much earlier in the development cycle. Shift-left is achieved successfully using this methodology as majority of defects are removed much earlier and software bringup-time on hardware has reduced from months to days!