2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS) 2021
DOI: 10.1109/dcis53048.2021.9666174
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Simulation of serial RRAM cell based on a Verilog-A compact model

Binbin Yang
1
,
D. Arumí
2
,
Salvador Manich
3
et al.
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