Simultaneous routing and buffering in floorplan design

Abstract

To deal with the floorplan design in a System-on-a-Chip (SOC), we have developed an EDA tool that simultaneuosly considers the problems of routing and buffer-insertion in floorplanning. This routing and buffering tool mainly contains a Manhattan routing (MR) algorithm and a maze-based between-buffer routing (MBR) algorithm. Since the processing speed of its MR is vety fast, this tool can he integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.