Single bit-line 7T SRAM cell for low power and high SNM

Madiwalar, B.; Kariyappa, B S

doi:10.1109/imac4s.2013.6526412

Cited by 27 publications

(9 citation statements)

References 6 publications

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“…This 6T based SRAM cell uses an additional power and gives poor stability at low supply voltage [12]. To overcome these limitations, 7T SRAM is designed where one NMOS transistor (T7) is added in the conventional 6T SRAM, which is positioned between the two (I1 and I2) cross-coupled inverters.…”

Section: Cmos Based Seven (7t) Transistors Static Ram Cellmentioning

confidence: 99%

Memristive Power Optimization of Non-volatile Seven Transistors Static Random Access Memory Cell

Jadon

Akashe

2015

Springer Proceedings in Physics

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Starting from the consecutive properties of Memristor, researchers identify that using a non-linear element "Memristor" into the circuit, the power consumption of the design will be reduced to a great extent. Memristor acts as a conventional resistor, but it has a memory which stores data in the form of resistance. A new Seven Transistors (7T) based Static Random Access Memory (SRAM) cell using memristors is designed in this manuscript that provides low power as well as non-volatile functionality to the cell. Such hybrid CMOSMemristor's combination gives robustness, consistency and higher functionality to the CMOS subsystem. With the proposed 7T SRAM circuit, we observed that the Average Power (0.234 µW), Total Power (10.08 µW), Static Power (20.83 pW) and Dynamic Power (0.01 µW) are reduced over the conventional 7T SRAM circuits. Different low-power optimization tools and device modeling were discovered to make more accurate power consumption calculations. There will be a need of designing such devices which are essential for the VLSI circuit designers. Memristor verifies itself to be a strong contender for the growing demands of Low power and Portable applications. Simulation of the SRAM design has been done in a 45 nm CMOS environment with the help of Cadence Virtuoso tool, and the recorded results depicted the advantages of proposed design over the CMOS based SRAM cell.

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Section: Cmos Based Seven (7t) Transistors Static Ram Cellmentioning

confidence: 99%

Memristive Power Optimization of Non-volatile Seven Transistors Static Random Access Memory Cell

Jadon

Akashe

2015

Springer Proceedings in Physics

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“…Table 1 shows the power dissipation for various operations in 6T and 7T SRAM cells [8]. Similarly, Table 2 shows delay for various operations in 6T and 7T SRAM cells [8]. Table 3 shows the power delay product of different SRAM cells at V DD = 1.32V in 90nm CMOS technology [9].…”

Section: Performance Comparison Of Different Sram Cellsmentioning

confidence: 99%

“…Finally, conclusion is provided in section IV. Fig.1 shows a 6T SRAM cell [8]. This SRAM cell shows poor stability and has small hold and read static noise margins.…”

Section: Introductionmentioning

confidence: 99%

“…This SRAM cell provides less read noise margin which further degrades due to process variation. To achieve higher read noise margin in 6T SRAM cell, width of pull down transistors has to be increased which eventually increases the issue of rise in leakage power dissipation [8]. This SRAM cell consumes more power and shows poor stability for small feature sizes with low voltage supply.…”

Section: Introductionmentioning

confidence: 99%

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Performance Comparison for Different Configurations of SRAM Cells

Sah¹,

Hussain²,

Kumar³

2015

IJIRSET

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ABSTRACT:Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today's memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other configurations because this structure uses a single bit for both read and write operations. This SRAM cell also provides the least power delay product among different studied SRAM configurations. Performance in terms of power dissipation and power delay product are least for 7T SRAM cell among the other SRAM configurations in 90nm CMOS technology.

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“…For instance, the use of new devices such as FinFETs that leads to a significant performance improvement [2][3][4][5]. At the cell level, new cells such as 7T, 8T, 9T, 10T, and 11T [6][7][8][9][10][11][12] have been proposed with the focus on improving read static noise margin (RSNM) or write margin (WM). At the architecture level, proposed read and write assist techniques in literature can improve SRAM robustness and performance while occupying less area compared to the cell techniques (e.g.…”

Section: Introductionmentioning

confidence: 99%

Improved read and write margins using a novel 8T-SRAM cell

Moradi

Madsen

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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This paper presents a novel subthreshold 8T-SRAM for ultra-low power applications. The proposed SRAM cell improves write margin by at least 22% to the standard 6T-SRAM cell at supply voltage of 1V compared. Furthermore, read static noise margin is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed SRAM cell, the total leakage power is increased for superthreshold regions, the proposed cell is able to work at supply voltages lower than 200mV with significantly improved robustness without any leakage increase. The proposed SRAM design improves write margin of the SRAM cell in comparison to the standard 7T-SRAM cell. The proposed circuit is designed in TSMC 65nm CMOS technology.

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Single bit-line 7T SRAM cell for low power and high SNM

Cited by 27 publications

References 6 publications

Memristive Power Optimization of Non-volatile Seven Transistors Static Random Access Memory Cell

Memristive Power Optimization of Non-volatile Seven Transistors Static Random Access Memory Cell

Performance Comparison for Different Configurations of SRAM Cells

Improved read and write margins using a novel 8T-SRAM cell

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