Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

Fan, Ming-Long; Yang, Shan-Yi; Hu, Vita Pi‐Ho; Chen, Yin Nien; Su, Pin; Chuang, Ching Te

doi:10.1016/j.microrel.2013.12.026

Cited by 25 publications

(18 citation statements)

References 56 publications

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“…In this section, we applied the Dual-Point method to explore the VG dependence of the RTN magnitude. By convention [9], the RTN magnitude is defined as ΔID/ID0 under constant VG, where ID0 is the drain current with the single trap at its empty state. ΔID/ID0 against VG from multiple nano-scaled p-and n-FETs are shown in Fig.5a&b respectively.…”

Section: Applications To Rtn Study In Nano-scaled Devicementioning

confidence: 99%

“…However, the standard RTN procedure [4] only captures the current under constant gate voltage, VG_RTN, which contains limited information. Understanding the entire ID-VG curve and its shift induced by the Random Telegraph Noise (RTN) can provide valuable information in understanding its underlying physical mechanism [5][6][7] and also in the circuit simulation for the time-dependent variability prediction [8,9]. Usually such measurement is carried out by repeating the standard RTN test procedure under different VG levels [10,11].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Dual-Point Technique for the Entire I_D–V_G Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

Zhan

Shen

et al. 2019

IEEE Electron Device Lett.

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A simple Dual-Point technique to measure the entire transfer characteristics (ID-VG) down to sub-threshold region in the nano-scaled MOSFET under Random Telegraph Noise (RTN) condition with either capturing or emitting one elementary charge by a trap in the gate dielectric is proposed. Its compatibility with the commercial semiconductor analyzer makes it a readily-usable tool for future RTN study. In this work, we use this technique to explore the VG dependence of RTN induced by a single trapped carrier in both n-and p-FETs.

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Section: Applications To Rtn Study In Nano-scaled Devicementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Dual-Point Technique for the Entire I_D–V_G Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

Zhan

Shen

et al. 2019

IEEE Electron Device Lett.

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“…Our investigations focus on the change in the

I_{D}

induced by the trapping of an individual electron in an acceptor type interface state at the Si/SiO 2 interface in n‐FinFET. The analysis is done for n‐type FET hence a negatively charged trap is placed at the Si/SiO 2 interfaces to simulate the altered drain current [9]. Simulation is carried out for different trap positions (at mid‐channel at the top, front and back gates).…”

Section: Single Charge Trapping Analysismentioning

confidence: 99%

“…They determine the dynamic current due to trapping and de-trapping of charge carriers. Further, he did the SCT analysis for tunnel FinFET with varying WF, it extended for FinFET, Si/Fe nanowire field-effect transistors (FETs) [9]. Artola et al [10] also found that SCTs become a major source of reliability losses.…”

Section: Introductionmentioning

confidence: 99%

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

Yadav

Shah

Beohar

et al. 2019

Micro & Nano Letters

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High-k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short-channel effects in scaled devices. The work presents a high-performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low-k and outer high-k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high-k spacer width of the SCT tolerant design. SCT analysis is presented in different high-k spacer materials and back-gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.

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“…Random Telegraph Noise (RTN) has attracted increasing attentions with the scaling roadmap of device dimension. In the ultra-scaled devices, random dopant fluctuation (RDF) and electrical traps in the gate dielectrics cause significant time-zero and time-dependent variation issues [1]- [3]. RTN induced variability is observed as the randomly drain current fluctuation under the constant gate and drain voltage, of which the parameters are characterized within a certain time, i.e., a measurement window [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Dual-Point Technique for Multi-Trap RTN Signal Extraction

Zhan

Wang

et al. 2020

IEEE Access

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Random telegraph noise (RTN), as one dominant variation source in the ultra-scaled devices, has been attracting much more attention, and its analysis is of great importance to understand the fundamental physical mechanisms. In this work, with the advanced dual-point method, we successfully separate the impacts of each trap in multi-traps correlated RTN, especially for complex anomalous RTN signals. A four-level transfer curve and VG-dependent RTN magnitude are extracted in a two-trap transistor from the sub-threshold region to the linear region. Furthermore, current degradations contributed from each trap of three-and four-level RTN signals are identified and distinguished. The proposed method can be utilized to evaluate multiple traps RTN and explore the underlying physics.

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Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

Cited by 25 publications

References 56 publications

A Dual-Point Technique for the Entire I_D–V_G Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

A Dual-Point Technique for the Entire I_D–V_G Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

Dual-Point Technique for Multi-Trap RTN Signal Extraction

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Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

Cited by 25 publications

References 56 publications

A Dual-Point Technique for the Entire ID–VG Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

A Dual-Point Technique for the Entire ID–VG Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

Dual-Point Technique for Multi-Trap RTN Signal Extraction

Contact Info

Product

Resources

About

A Dual-Point Technique for the Entire I_D–V_G Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

A Dual-Point Technique for the Entire I_D–V_G Characterization Into Subthreshold Region Under Random Telegraph Noise Condition