Sinusoidal Signal Generation Through Successive Integration

Ibrahim, Mahmoud A. A.; Onabajo, Marvin

doi:10.1109/iscas.2019.8702090

Cited by 7 publications

(4 citation statements)

References 37 publications

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“…In practice, an amplitude control loop would be required to inject a calibration current at the drains of transistors MP and MN in Fig. 4 to compensate for process corner, temperature, and supply voltage variations similar to [20]- [22]. The designed filter was simulated for all possible combination of process corners (TT, SS, and FF) supply voltages (595 mV, 600 mV, and 605 mV; assuming ± 5 mV fluctuation) and temperatures (-25 ºC, 10 ºC, and 85 ºC ).…”

Section: Measurement Resultsmentioning

confidence: 99%

Analysis and Experimental Validation of Large-Signal Linearization for Low-Power Complex OTA-C Filters

Jha

Ibrahim

Onabajo

2021

IEEE Open J. Circuits Syst.

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This paper presents a second-order complex baseband operational transconductance amplifier-capacitor (OTA-C) filter design for wireless receivers. It employs a novel adaptive biasing circuit for large-signal linearization that extends the filter's usable signal swing range. An analysis of this linearization technique provides insights into its underlying concepts to assist the design process. The method is demonstrated with the first experimental evaluation of a second-order complex baseband filter prototype having a center frequency of 2 MHz and a bandwidth of 850 KHz. Fabricated in a standard 130nm CMOS technology, the filter prototype measurement results show a gain of 35.1 dB and an image rejection ratio of 39.7 dB while operation from a supply voltage of 0.95 V and consuming 0.13 mA. This design advances the low-power bandpass filter state-of-the-art by having an in-band and out-of-band SFDR of 62 dB and 64 dB respectively due to the use of the large-signal linearization approach.

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Section: Measurement Resultsmentioning

confidence: 99%

Analysis and Experimental Validation of Large-Signal Linearization for Low-Power Complex OTA-C Filters

Jha

Ibrahim

Onabajo

2021

IEEE Open J. Circuits Syst.

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“…CT filters have been widely adopted in on-chip SSGs [35], [36], [38], [39], [44], [45], [47], [51], [52], [59], [62], [63], [73], [101], [102]. The most simple but fundamental CT filter is passive RC LPFs.…”

Section: A Linearity Enhancement In Ct Domainmentioning

confidence: 99%

“…Alternatively, active g m -C filters have been adopted for decreasing the minimum f SG with small die area [38], [39], [44], [51], [52], [59], [73], [101], [102]. Fig.…”

Section: A Linearity Enhancement In Ct Domainmentioning

confidence: 99%

“…For example, in [73], to generate a sinusoidal signal with THD = 1.40% and SFDR = 36.67 dB from the 50%-duty square waveform, a high-order g m -C filter which consists of 12 g m cells and 6 capacitors is required. Similarly in [102], a high-order CT filter, which cascades seven g m -C integrators coupled with high-pass filters between the stages, is adopted to achieve THD of -51 dBc and SFDR of 51 dB from the 50%-duty square waveform.…”

Section: A Linearity Enhancement In Ct Domainmentioning

confidence: 99%

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On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

Kweon¹,

Rafi

Cheon

et al. 2022

IEEE Trans. Biomed. Circuits Syst.

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This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material's impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform's frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.

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A 0.05%–0.08% THD, 762.9 Hz–10 MHz direct digital frequency synthesizer using a reconfigurable DAC for electrochemical impedance spectroscopy measurements

Farouk,

Dessouky,

Naguib

2024

Circuit Theory & Apps

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SummaryA wide‐range direct digital frequency synthesizer (DDS) is considered an essential component that is used in measuring electrochemical impedance spectroscopy (EIS). Since it depends on exciting the electrochemical sensor by a pure sine wave, total harmonic distortion (THD) is considered a challenging specification for an accurate EIS measurement. This paper introduces a complete system and circuit designs of a wide range DDS with a comprehensive system model using MATLAB environment. In addition, it presents the usage of a reconfigurable digital‐to‐analog converter (DAC) on the circuit level that is used either as a 4‐bit delta‐sigma ( ) DAC or an 8‐bit binary‐weighted DAC for both low‐ and high‐frequency ranges, respectively. The designed DDS generates an output frequency range from 762.933 Hz to 10 MHz using a physical 8‐bit DAC. The circuits are simulated using 0.18 μm CMOS technology. The designed DDS system achieves THD less than 0.05% with superior free dynamic range (SFDR) 66 dBc for low‐frequency range and 0.08% with SFDR 62 dBc for high‐frequency range. The DDS circuits occupy an area of 400 × 800 μm. The whole system consumes a 2.5 mW power consumption from a 1.8 V supply.

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Sinusoidal Signal Generation Through Successive Integration

Cited by 7 publications

References 37 publications

Analysis and Experimental Validation of Large-Signal Linearization for Low-Power Complex OTA-C Filters

Analysis and Experimental Validation of Large-Signal Linearization for Low-Power Complex OTA-C Filters

On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

A 0.05%–0.08% THD, 762.9 Hz–10 MHz direct digital frequency synthesizer using a reconfigurable DAC for electrochemical impedance spectroscopy measurements

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