Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

Abstract

The sizes of the metal-oxide-semiconductor (MOS) transistors in an operational amplifier must guarantee strong direct current operating point (DCOP) conditions. This paper shows the usefulness of two population-based optimization algorithms to size transistors, namely—particle swarm optimization (PSO) and many optimizing liaisons (MOL). Both optimization algorithms link the circuit simulator SPICE to measure electrical characteristics. However, SPICE provides an output-file indicating that a transistor is in strong inversion but the DCOP can be in the limit, and it can switch to a different condition. In this manner, we highlight the application of PSO and MOL to size operational transconductance amplifiers (OTAs), which DCOP conditions are improved by the introduction of a procedure that handles constraints to ensure that the transistors are in the appropriate DCOP. The Miller and RFC-OTA are the cases of study, and their sizing is performed using UMC 180 nm CMOS technology. In both OTAs, the objective function is the maximization of the gain-bandwidth product under the main constraint of guaranteeing DCOPs to improve two figures of merit and to provide robustness to Monte Carlo simulations and PVT variations.

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

“…Note that different objective functions and constraints other than ( 7) can be used. For example, [28] defines a new kind of Figure of Merit. ESSAB applies to any objective functions and constraints.…”

“…Instead, it aims at addressing the above two key challenges when introducing machine learning techniques into optimization-based analog IC sizing. Important research topics such as sizing problem definition assessing the merit of designs, yield optimization considering process, voltage and temperature variations [28] are out of the scope but compatible with ESSAB.…”

CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators

“…For instance, the OTAs require high differential gain, high gain-bandwidth product, and the best linearity as possible [34]. In addition, an OTA must be robust to PVT and Monte Carlo variations [35]. This section details the design of the blocks required to implement the proposed OTA-based FOCO 1 shown in Figure 6 and FOCO 2 shown in Figure 8, by using CMOS technology of 180 nm from UMC.…”

“…The sizes of the CMOS OTA, to provide a gm = 500 µA/V and gm = 350 µA/V, are shown in Table 1 by using a load capacitor of C L = 220 pF. The table lists the direct current (DC) gain in decibels (dB), gain-bandwidth (GBW) in kilo hertz (KHz), phase margin (PM) in degrees ( • ), common-mode rejection ration (CMRR) in dB, slew rate (SR) in volt/ µs, power supply rejection ratio (PSRR), power dissipation in milliwatts, the small and large-signal figures of merit (FoM) from [35], the width (W) and length (L) of the MOS transistors in micro-meters, and the bias current (Ib).…”

A Refinement of Recurrence Analysis to Determine the Time Delay of Causality in Presence of External Perturbations

“…Zhao et al then showed the reciprocal characterization of time series and multilayer networks and introduced the concept of interlayer entropy between two quantities aimed at measuring the strength of interrelationships from one layer to another, demonstrating that in networks it is the equivalent of transfer entropy in time series [ 10 ]. In telecommunication and electronics, integrated circuits and their design [ 11 ], both due to the wide range of dynamics that can be explored and to the huge amount of complex data that can be produced, represent an interesting field of research for many applied oriented studies like chaos-based secure communications [ 12 ] using the so called snap circuits.…”