SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

Gammie, Gordon; Wang, A.; Mair, Hugh; Lagerquist, Rolf; Chau, Minh Quang; Royannez, Philippe; Gururajarao, S.; Ko, Uming

doi:10.1109/jproc.2009.2034684

Cited by 33 publications

(25 citation statements)

References 17 publications

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“…Gammie et al [3] discuss 'SmartReflex' power management technology used by Texas Instruments mobile processors, such as 90nm OMAP2420 processor [141], 65 nm OMAP3430 processor [142] and the 45 nm 3.5 G Baseband and Multimedia Application Processor [143]. For saving both dynamic and leakage energy in SRAM, these processors use techniques such as state-preserving and state-destroying leakage control, voltage scaling etc.…”

Section: Cache Energy Saving In Real-world Chipsmentioning

confidence: 99%

“…For several reasons, managing energy consumption of caches is a crucial issue in modern processor design. With each CMOS (complementary metal oxide semiconductor) technology generation, there is a significant increase in the leakage energy consumption [2], [3]. According to the estimates of International Technology Roadmap for Semiconductors (ITRS); with technology scaling, leakage power consumption will become a major industry crisis, threatening the survival of CMOS technology itself [4].…”

Section: Introductionmentioning

confidence: 99%

“…We highlight the basis of similarities and differences between the techniques. Since leakage energy is becoming an increasing fraction of cache power consumption [2], [3], [59], we focus more on leakage energy saving techniques than dynamic energy saving techniques. Section V discusses the approaches which are used for saving both dynamic and leakage energy.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A survey of architectural techniques for improving cache power efficiency

Mittal

2014

Sustainable Computing: Informatics and Systems

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Section: Cache Energy Saving In Real-world Chipsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A survey of architectural techniques for improving cache power efficiency

Mittal

2014

Sustainable Computing: Informatics and Systems

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“…Power gating is one of widely employed techniques that are available in VLSI design [9][10][11]. Power gating technique employs high-th sleep transistors between the lowth functional block and supply/ground rails.…”

Section: Introductionmentioning

confidence: 99%

A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Fan

Dong

et al. 2014

Journal of Electrical and Computer Engineering

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With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper.

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“…To support Adaptive Voltage Scaling (AVS) and split/dual rail architectures, the input array (VDDAR) and periphery (VDDPR) voltages can vary independently. The dummy decoders and delay generators can't be easily designed to match this voltage/process variation because the normal read access traverses array and periphery domains through the decoder (on VDDPR), Wordline driver + Level shifter (on VDDPR/VDDAR), bitcell (on VDDAR/VDDPR) etc.In case of Retain till Access (RTA) SRAMs [2,3], an extra component of RTA switch/diode circuit variation needs to be margined into the design robustness. In the absence of suitable matching between replica and normal access, additional timing margin addition is resorted to, thereby leading to a sub-optimal performance.…”

mentioning

confidence: 99%

A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit

Gupta

Rana

2012

2012 International SoC Design Conference (ISOCC)

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we propose an SRAM replica tracking circuit that reduces divergence of the replica path relative to normal read path (6-16% less Sense differential Requirement), thus improving the access time by 5-8%. The approach is compatible to power managed SRAMs having Retain till Access feature and also for non power managed SRAMs with no sense differential impact. Using This Replica tracing circuit Sense differential has been well tracked across all array and periphery voltages combinations which further improve the access time by 4-6%. Instances with this method 0.5-256Kb have been tested on a 28nm CMOS LP process. I.CONVENTIONAL TRACKING SCHEME Conventional SRAM replica tracking circuits impose penalty on read access/cycle time due to inclusion of dummy decoders and delay generators in the replica path for tracking wordline/bitline path delays across operating conditions [1]. With the prevalence of split rail architectures for SRAM for bitcell assist [2-3], tracking circuits need to work robustly across a combination of array/periphery voltages and process variations. Hence reducing divergence of tracking path compared to a normal read/write access path (that traverses both array and periphery voltage domains) is key to obtaining performance in split rail memories. In this work, an SRAM in low-power 28nm CMOS is built with 0.12ȝm2 bitcells [6] and uses a replica tracking circuit that provides lower divergence for the Wordline path across operating conditions. Figure 1 shows a conventional tracking circuit that uses dummy decoders and delay generators in the replica path. To support Adaptive Voltage Scaling (AVS) and split/dual rail architectures, the input array (VDDAR) and periphery (VDDPR) voltages can vary independently. The dummy decoders and delay generators can't be easily designed to match this voltage/process variation because the normal read access traverses array and periphery domains through the decoder (on VDDPR), Wordline driver + Level shifter (on VDDPR/VDDAR), bitcell (on VDDAR/VDDPR) etc.In case of Retain till Access (RTA) SRAMs [2,3], an extra component of RTA switch/diode circuit variation needs to be margined into the design robustness. In the absence of suitable matching between replica and normal access, additional timing margin addition is resorted to, thereby leading to a sub-optimal performance. Figure.1 Conventional SRAM replica tracking circuit II. PROPOSED TRACKING SCHEMEMultiple methods have been discussed in literature to counter the effects of variation on replica paths [4,5]. A commercially viable solution however needs a simple yet effective tracking method that reduces the variation impact on performance, yet does not require post fabrication calibration involving additional tester time for every chip. The key improvements of the proposed tracking method over prior art are:a.) the commonality of the normal access and replica path from the CLK to Wordline (CLK2WL) generation b.) the replica wordline generator circuit c.) the ability of the replica circuit to track variation across all per...

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SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

Cited by 33 publications

References 17 publications

A survey of architectural techniques for improving cache power efficiency

A survey of architectural techniques for improving cache power efficiency

A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit

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