Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs

Kuentzer, Felipe A.; Krstić, Miloš

doi:10.1109/tcsi.2020.2998911

Cited by 14 publications

(2 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Pulsar [14] departs from this paradigm. It supports, for example, an asynchronous ST template called Spatially-Distributed Dual Spacer Null Convention Logic (SDDS-NCL) 2 . SDDS-NCL enables the use of commercial EDA tools from e.g.…”

Section: Contributions Of This Workmentioning

confidence: 99%

“…Uncertainties indeed affect the circuit design process. Increasing manufacturing process variations have to be more carefully considered, together with environmental conditions such as voltage supply and temperature variations [1], maybe even added with accounting for ionising radiation incidence during circuit operation [2]. Besides, design concerns such as IR drop [3] 1 and long wire delays become more relevant.…”

Section: Introduction and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Components to Support Choice in Self-Timed Asynchronous Design Flows

Sartori

Nunes

Calazans

2023

JICS

View full text Add to dashboard Cite

The design of digital circuits on recent technologies brings several challenges, among which robustness to variations stands out. Variation sources are multiple, and the evolution of integrated circuit fabrication techniques increases the number and relevance of such sources, and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations of one or more types. Asynchronous self-timed design is one such paradigm that can provide robustness to process, voltage, temperature, ageing and IR drop variations, to cite some of the main types. This paper proposes an enhancement to the Pulsar environment, a recently proposed open source automated flow for the design of self-timed clockless circuits.The six components proposed here enable describing choices and decisions on the flow of data tokens inside asynchronous circuits.Design capture in Pulsar can then employ these. To implement the abstract (synthesis-enabled) components, the paper also bringsthe proposal of the handshaking mutex, a versatile complex gate that eases the design of probe and arbiter, the two most complex among the new components. Results demonstrate the new version of Pulsar is more powerful than the previous, baseline, version, enabling the design capture and the automated synthesis steps of more complex asynchronous self-timed circuits. They also indicate the handshaking mutex operates correctly, and with a good level of attested fairness.

show abstract

Section: Contributions Of This Workmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%