Software Implementation and Comparison of ZUC-256, SNOW-V, and AES-256 on RISC-V Platform

Wei, Mengmeng; Yang, Guoqiang; Kong, Fanyu

doi:10.1109/icicse52190.2021.9404134

Cited by 8 publications

(2 citation statements)

References 8 publications

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“…Figures 2, 4, and 7, Figures S1 and S2 in Supporting Information S1 were made with Matplotlib version 3.5.2 (Caswell et al, 2022;Hunter, 2007), available under the Matplotlib license at https://matplotlib.org/. Statistical analysis, machine learning and Figure 6 were based on R platform (Fortmann-Roe, 2015;Liaw and Wiener, 2022;Ripley et al, 2022;Wei et al, 2021).…”

Section: Discussionmentioning

confidence: 99%

Quantifying the Spatial Representativeness of Carbon Flux Footprints of a Grassland Ecosystem in the Semi‐Arid Region

Gong

Wang

et al. 2023

JGR Atmospheres

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Anthropogenic carbon dioxide (CO 2 ) emissions have been increasing rapidly since the industrial revolution, causing global warming and environmental change. CO 2 emissions in arid regions are only 30% of those in humid regions, but the warming rate is 20%-40% higher than that of humid regions (Yao et al., 2020). Such a significant spatial heterogeneity in warming rate and CO 2 emissions causes arid regions to face greater climate hazards than humid regions (Huang et al., 2012(Huang et al., , 2019Yao et al., 2020), and increasingly frequent and severe droughts threaten the ability of dryland ecosystems to sequester carbon and maintain biodiversity (Yao et al., 2020). Therefore, it is

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Section: Discussionmentioning

confidence: 99%

Quantifying the Spatial Representativeness of Carbon Flux Footprints of a Grassland Ecosystem in the Semi‐Arid Region

Gong

Wang

et al. 2023

JGR Atmospheres

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“…The work by Hao Cheng et al [17] provided the completed fundamental analysis, design, implementation results, hardware, and software of an ISE (instruction set extension) for 10 lightweight cryptography algorithms. In addition to utilizing the C programing language for pure software implementations [18], it seemed that the preferred implementation approach also involved using an ISE. The work [19] introduced a lightweight ISE designed to support the ChaCha stream cipher in RISC-V architectures, which achieved a speedup gain of at least 5.4 times compared to the OpenSSL baseline and 3.4 times compared to an ISA optimized implementation.…”

Section: Related Workmentioning

confidence: 99%

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Pham

et al. 2023

Future Internet

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The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

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AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

Choi,

Park,

Han

et al. 2024

Engineering Science and Technology, an International Journal

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Software Implementation and Comparison of ZUC-256, SNOW-V, and AES-256 on RISC-V Platform

Cited by 8 publications

References 8 publications

Quantifying the Spatial Representativeness of Carbon Flux Footprints of a Grassland Ecosystem in the Semi‐Arid Region

Quantifying the Spatial Representativeness of Carbon Flux Footprints of a Grassland Ecosystem in the Semi‐Arid Region

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

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