Software Implementation of WiMAX on the Sandbridge SandBlaster Platform

Iancu, Daniel; Ye, Hua; Senthilvelan, Murugappan; Glossner, John; Surducan, Vasile; Kotlyar, Vladimir; Iancu, Andrei; Nacer, Gary; Takala, Jarmo

doi:10.1007/11796435_44

Cited by 7 publications

(5 citation statements)

References 5 publications

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“…The use of general-purpose processor (GPP) and DSPs were addressed in [22,23] and [24], respectively. However, the results show that these implementations are not power efficient for high-speed data rates.…”

Section: Development Platforms For Ofdm Transceivers: a Reviewmentioning

confidence: 99%

The implementation of the clustered‐OFDM‐based transceiver on an FPGA device: A comprehensive comparison

et al. 2021

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Aiming at reducing hardware complexity and power consumption of multicarrier-based broadband transceivers, this contribution discusses and analyzes the implementation of clustered-orthogonal frequency division multiplexing (OFDM)-based transceiver in a field programmable gate array (FPGA) device. In this sense, several OFDM schemes covering baseband and passband data communications are implemented. The hardware resource utilization and power consumption related to each scheme, after being implemented in the FPGA device, are discussed and compared. Numerical results show that the OFDM scheme based on  (⋅)-II and (⋅)-III, which is a modified version of the hermitian symmetric (HS)-OFDM scheme, which performs both baseband and passband data communications, demands the lowest hardware resource utilization and power consumption, reducing to 1/3 the hardware resource utilization. As a result,  (⋅)-II and (⋅)-III constitute an interesting candidate for implementing new generations of high data rate, low hardware resource utilization, and low-power consumption clustered-OFDM-based transceivers for broadband data communication. Last but not least, numerical results show that the controllers used to integrate all components of a clustered-OFDM-based transceiver can demand sizeable hardware resource utilization and power consumption and, therefore, they have to be carefully designed. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Development Platforms For Ofdm Transceivers: a Reviewmentioning

confidence: 99%

The implementation of the clustered‐OFDM‐based transceiver on an FPGA device: A comprehensive comparison

et al. 2021

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“…All of the processing blocks are executed entirely in software. Detailed description of the implementation is available in an earlier paper 8 .…”

Section: Wimax Systemmentioning

confidence: 99%

“…The WiMAX transmit and receive algorithms are implemented as concurrent multithreaded pipelines 8 . The pipelines consist of all the processing steps such as FFT, filtering, scrambling, etc.…”

Section: Real Time Implementationmentioning

confidence: 99%

Hand held analog television over WiMAX executed in SW

Iancu¹,

Ye²,

Senthilvelan³

et al. 2007

SPIE Proceedings

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This paper describes a device capable of performing the following tasks: it samples and decodes the composite video analog TV signal, it encodes the resulting RGB data into a MPEG-4 stream and sends it over a WiMAX link. On the other end of the link a similar device receives the WiMAX signal, in either TDD or FDD mode, decodes the MPEG data and displays it on the LCD display. The device can be a hand held device, such as a mobile phone or a PDA. The algorithms for the analog TV, WiMAX physical layer, WiMAX MAC and the MPEG encoder/decoder are executed entirely in software in real time, using the Sandbridge Technologies' low power SB3011 digital signal processor. The SB3011 multithreaded digital signal processor includes four DSP cores with eight threads each, and one ARM processor. The execution of the algorithms requires the entire four cores for the FDD mode. The WiMAX MAC is executed on the ARM processor.

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“…More recently, there has been work on platforms that have higher peak performance due to increased parallelism in the form of multiple processor cores and SIMD vector extensions [9,10]. Reference [9] presents a software implementation of IEEE 802.16e (WiMAX) on the Sandbridge Sandblaster platform that consists of four DSP cores with SIMD arithmetic units.…”

Section: Introductionmentioning

confidence: 99%

“…Reference [9] presents a software implementation of IEEE 802.16e (WiMAX) on the Sandbridge Sandblaster platform that consists of four DSP cores with SIMD arithmetic units. The code achieves real-time for data rates up to 2.9 Mbit/s in WiMAX, which is functionally similar to WiFi.…”

Section: Introductionmentioning

confidence: 99%

Real-time software implementation of an IEEE 802.11a baseband receiver on Intel multicore

Berger

Arbatov

Voronenko

et al. 2011

2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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We present a software-only implementation of an IEEE 802.11a (WiFi) receiver optimized for Intel multicore platforms. The receiver is about 50 times faster than a straightforward C implementation, i.e., an implementation that has the same functionality, but leaves optimization completely to the compiler. Our hand-optimized implementation achieves real-time for all data rates up to the maximum of 54 Mbit/s on a Core i7, clocked at 3.3 GHz, and for up to 12 Mbit/s on an Atom, clocked at 1.6 GHz, using two cores in both cases. To achieve this performance we use up to two threads, up to 16-way vectorization using Intel's SSE, and various other optimizations.

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Software Implementation of WiMAX on the Sandbridge SandBlaster Platform

Cited by 7 publications

References 5 publications

The implementation of the clustered‐OFDM‐based transceiver on an FPGA device: A comprehensive comparison

The implementation of the clustered‐OFDM‐based transceiver on an FPGA device: A comprehensive comparison

Hand held analog television over WiMAX executed in SW

Real-time software implementation of an IEEE 802.11a baseband receiver on Intel multicore

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