Software model checking is a rich research field

Verification methodology for DEVS models

“…One o f the most successful techniques for systems formal verification is model checking [19]. In this method, the system to be verified is modeled by a suitable formalism such as I/O automata or TA, which can be represented in a graphical notation.…”

“…In Figure 9 [19]. The advantage of this technique is that it is fully automated and does not need human intervention to reveal errors in system design.…”