SP&amp;R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm

Park, Dong-Won; Lee, Daeyeal; Kang, Ilgweon; Gao, Sicun; Lin, Bill; Cheng, Chung‐Kuan

doi:10.1109/asp-dac47756.2020.9045729

Cited by 15 publications

(16 citation statements)

References 19 publications

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“…Given cell netlist and layout specification, our framework formulates an integrated constraint satisfaction problem (CSP) so that the automated cell layout simultaneously/strictly satisfies all constraints, which are transistor placement, in-cell routing, conditional design rules and pin-accessibility-driven constraints. Inspired by [15], individual constraints are combined by our novel dynamic pin shape and allocation constraint (i.e., DCPA). To ensure the mutability, our framework maximizes PS (Pin separation) and minimizes M2 Track use including objectives of [15] (i.e., Cell Size and Metal Length) through the lexicographic ordered optimization.…”

Section: Simultaneous Place-and-route For Cfet Sdc Synthesis Frameworkmentioning

confidence: 99%

“…Inspired by [15], individual constraints are combined by our novel dynamic pin shape and allocation constraint (i.e., DCPA). To ensure the mutability, our framework maximizes PS (Pin separation) and minimizes M2 Track use including objectives of [15] (i.e., Cell Size and Metal Length) through the lexicographic ordered optimization. We utilize five representative conditional design rules of [13,14], which are minimum area rule (MAR), end-of-line (EOL), via rule (VR), and multi-patternaware design rules (i.e., PRL (Parallel Run-Length)!SHR (Step Height Rule)).…”

Section: Simultaneous Place-and-route For Cfet Sdc Synthesis Frameworkmentioning

confidence: 99%

“…DCPA dynamically constructs the shared and split pin-shapes of FETs in the abstract pin interface (API) for an optimal in-cell routing exploration of a CFET structure. The dynamic pin allocation (DPA) scheme for simultaneous place-and-route follows the same principle of [15] for interconnecting placement and routing formulas using flow capacity variables (i.e., C~ (p, r) ). Figure 4 illustrates the concept ofDCPA.…”

Section: Dynamic Complimentary Pin Allocationmentioning

confidence: 99%

“…The Conv. SDCs are generated using the framework in [15]. For the fair comparison in terms of our metrics, we adopt the same in-cell horizontal routing tracks (i.e., 4 tracks) and push the SDC power rail to BPR layer for Conv.…”

Section: Cfet Vs Conv Cell Layoutmentioning

confidence: 99%

“…For multi-patterning technology nodes, [7,10,12] proposed SDC synthesis automation, but the placement and routing are performed in separate operations. Recently, in [15], they integrate the placement and routing with dynamic pin allocation (DPA) interface using Satisfiability Modulo theories (SMT) [1]. However, these works focus on the Conv.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

Cheng

Lee

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Simultaneous Place-and-route For Cfet Sdc Synthesis Frameworkmentioning

confidence: 99%

Section: Simultaneous Place-and-route For Cfet Sdc Synthesis Frameworkmentioning

confidence: 99%

Section: Dynamic Complimentary Pin Allocationmentioning

confidence: 99%

Section: Cfet Vs Conv Cell Layoutmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

Cheng

Lee

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

Self Cite

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Generalized Optimization Modulo Theories

Tsiskaridze,

Barrett,

Tinelli

2024

Lecture Notes in Computer Science

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Optimization Modulo Theories (OMT) has emerged as an important extension of the highly successful Satisfiability Modulo Theories (SMT) paradigm. The OMT problem requires solving an SMT problem with the restriction that the solution must be optimal with respect to a given objective function. We introduce a generalization of the OMT problem where, in particular, objective functions can range over partially ordered sets. We provide a formalization of and an abstract calculus for the Generalized OMT problem and prove their key correctness properties. Generalized OMT extends previous work on OMT in several ways. First, in contrast to many current OMT solvers, our calculus is theory-agnostic, enabling the optimization of queries over any theories or combinations thereof. Second, our formalization unifies both single- and multi-objective optimization problems, allowing us to study them both in a single framework and facilitating the use of objective functions that are not supported by existing OMT approaches. Finally, our calculus is sufficiently general to fully capture a wide variety of current OMT approaches (each of which can be realized as a specific strategy for rule application in the calculus) and to support the exploration of new search strategies. Much like the original abstract DPLL(T) calculus for SMT, our Generalized OMT calculus is designed to establish a theoretical foundation for understanding and research and to serve as a framework for studying variations of and extensions to existing OMT methodologies.

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Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node

Jeong,

Shin,

Lee

et al. 2024

IEEE Access

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SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm

Cited by 15 publications

References 19 publications

A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

Generalized Optimization Modulo Theories

Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node

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