Speed optimization of a FPGA based modified viterbi decoder

Chakraborty, D.; Raha, Prasun K.; Bhattacharya, Arijit; Dutta, Ritam

doi:10.1109/iccci.2013.6466245

Cited by 13 publications

(3 citation statements)

References 9 publications

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“…For RSA we found different FPGAs' implementations such as efficient or accelerated architectures [424][425][426], side-channel attacks resistant [427,428], tiny footprint [429] and Vedic mathematics based implementation [430]. Other cryptography techniques implemented in FPGAs are the Viterbi decoder with reconfigurable capabilities [279], high speed Viterbi decoders [431,432], steam cipher chaos-based techniques [433][434][435][436] and lightweight block cipher [437][438][439].…”

Section: Cryptography Techniquesmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Section: Cryptography Techniquesmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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“…The bitwise XOR logical operation and addition processes are shown in Eqs. (5) and (6) respectively, while the full calculation is shown in Eq. (7).…”

Section: Efficient Processing Element (Pe)mentioning

confidence: 99%

“…Low-power issues are quite popular, hence many researches on this topic have been presented (e.g. [4][5][6][7][8]). Besides power consumption, researches have been done on speed performance [9] and area efficiency (e.g.…”

Section: Introductionmentioning

confidence: 99%

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Putra

Adiono

2016

J. ICT Res. Appl.

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Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and lowcomplexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

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Real-time area efficient and high speed architecture design of Viterbi decoder

Middya

Dhar

2016

2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEIC

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Speed optimization of a FPGA based modified viterbi decoder

Cited by 13 publications

References 9 publications

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array Applications—A Scientometric Review

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Real-time area efficient and high speed architecture design of Viterbi decoder

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