SSTL IO Standard Based Low Power Arithmetic Design Using Calana Kalanabhyam on FPGA

Verma, Gaurav; Shekhar, Sushant; Kant, Kumar Shashi; Verma, Vikas; Verma, Himanshu; Pandey, Bishwajeet

doi:10.14257/ijca.2016.9.4.27

Cited by 8 publications

(4 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These are Object Tracking [7], portable design [8] and digital signal processing [9]. Gaurav et al focuses on different low power techniques related to SSTL IO standards and various others [10,11,12]. Sakshi et al designed the green ECG machine using various logic families and compares them at different frequencies [13].…”

Section: Related Workmentioning

confidence: 99%

Smart Communication Network design with application of Energy Efficient Digital Clock for Monitoring of Time -To-Live (TTL)

Singhal¹,

Shrivastava²,

Jain³

et al. 2017

GJET

Self Cite

View full text Add to dashboard Cite

Abstract. We are using term smart in two contexts, one context it is able to monitor Time to Live (TTL) with integration of digital clock in network and other context is energy efficiency that comes with design of energy efficient digital clock using HSTL IO standards available on Virtex-5 FPGA. Digital clock will trigger alarm when it current value reaches nearer to TTL and alarm will continue when it goes beyond TTL. This work also deals with a research gap that electronics designer never bother about selection of Input Output Standards. Current researcher focus only on efficient coding but never focus on selection of energy efficient IO standards. After testing and implementation phase of digital clock, we conclude that HSTL-II is the most efficient in term of energy efficiency and HSTL-III18 is the least efficient in term of energy efficiency.

show abstract

Section: Related Workmentioning

confidence: 99%

Smart Communication Network design with application of Energy Efficient Digital Clock for Monitoring of Time -To-Live (TTL)

Singhal¹,

Shrivastava²,

Jain³

et al. 2017

GJET

Self Cite

View full text Add to dashboard Cite

show abstract

“…Singh and Sasamal [32] have presented a study where binary Vedic multiplier is implemented over cadence tool using adiabatic logic. Usage of another Vedic sutra called as Calana Kalanabhyam was seen in the work of Verma et al [33] where the authors have used it alongside with FPGA to make energy-efficient sutra. Vijayan et al [34] have presented a Vedic multiplier of 8-bits in FPGA.…”

Section: Related Workmentioning

confidence: 99%

ROI-based Compression on Radiological Image by Urdhva-Tiryagbhyam and DWT Over FPGA

Suma¹,

Sridhar²

2017

ijacsa

View full text Add to dashboard Cite

Abstract-The area of radiological image compression has not yet met its potential solution. After reviewing the existing mechanism of compression, it was found that majority of the existing techniques suffers from significant pitfalls e.g. more usage of transformation schemes, more resource utilization, delay, less focus on FPGA performance enhancement, extremely less emphasis on Vedic-multipliers. Hence, this paper presents an analytical modelling of ROI (Region of Interest)-based radiological image compression that applies Vedic Multiplier Urdhva-Tiryagbhyam to enhance the performance of coding using Discrete Wavelet Transform (DWT). The study outcome was implemented in Matlab and multiple test bed of FPGA devices (Virtex 4 FX100 -12 FF1152 and Spartan 3 XC400-5TQ144) and assessed using both visual and numerical outcomes to find that proposed system excel better performance in comparison to recently existing techniques.

show abstract

“…The data are handled by open frameworks. Encryption process changes data as structure closer and more sensible that depends on the investigation with no reasonable learning [1]. The objective behind this is to secure data by maintaining and keeping it away from illegal user access.…”

Section: Introductionmentioning

confidence: 99%

Low-power AES S-box design using dual-basis tower field extension method for cyber security applications

Nandan

Rao

2021

Complex Intell. Syst.

View full text Add to dashboard Cite

In cryptography, one among several investigated areas is the implementation of AES S-boxes. In this paper, a substitution-box is designed which follows combined data path using dual-basis tower field extension with Golod–Shafarevich theorem fed in immune genetic algorithm for optimization purpose for each and every block. The role of enhanced immune genetic algorithm is as follows: at first, chaotic system generates S-boxes population, these S-boxes which perform excellently are then optimized by a sequence of operators such as extraction of anti-agent and immune selection. Few criteria of S-boxes such as differential uniformity, nonlinear degree, and strict avalanche effect are analyzed. The obtained results are analyzed with CMOS 35 nm and 15 nm technologies to measure the performance of the proposed designs and was observed that the proposed one outperforms in power and area. The optimized S-box can be effectively applied for securing information. The proposed Golod–Shafarevich feeder Immune Genetic Algorithm S-box (GSIGA-Sbox) is compared with two baseline methods such as Reversed Genetic Algorithm S-box (RGA-Sbox) and Discrete Space Chaotic S-box (DSC-Sbox). As a result the proposed GSIGA-Sbox achieves encryption speed of 61 MHZ, decryption speed of 55 MHZ with 24% of power consumption for 35 nm CMOS technology and 57 MHZ encryption speed, 51 MHZ decryption speed with 28% of power consumption for 15 nm CMOS technology.

show abstract

SSTL IO Standard Based Low Power Arithmetic Design Using Calana Kalanabhyam on FPGA

Cited by 8 publications

References 10 publications

Smart Communication Network design with application of Energy Efficient Digital Clock for Monitoring of Time -To-Live (TTL)

Smart Communication Network design with application of Energy Efficient Digital Clock for Monitoring of Time -To-Live (TTL)

ROI-based Compression on Radiological Image by Urdhva-Tiryagbhyam and DWT Over FPGA

Low-power AES S-box design using dual-basis tower field extension method for cyber security applications

Contact Info

Product

Resources

About