STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies

Venkatesan, Rangharajan; Ramasubramanian, Shankar Ganesh; Venkataramani, Swagath; Roy, Kaushik; Raghunathan, Anand

doi:10.1109/isca.2014.6853233

Cited by 19 publications

(19 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We assume a NoC clock speed of 1GHz which allows SRAM, STT-MRAM, and Racetrack reads in a single cycle based on latency data from NVSIM and the literature [24]. STT-MRAM writes are also optimistically assumed to be a single cycle [15] similar to SRAM, while Racetrack shifts and writes take half a cycle allowing a Racetrack to conservatively write and shift, or shift twice in a cycle [24].…”

Section: Experimental Methodologymentioning

confidence: 99%

See 1 more Smart Citation

Domain-wall memory buffer for low-energy NoCs

Kline

Melhem

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

View full text Add to dashboard Cite

Networks-on-chip (NoCs) have become a leading energy consumer in modern multi-core processors, with a considerable portion of this energy originating from the large number of virtual channel (FIFO) buffers. While emerging memories have been considered for many architectural components such as caches, the asymmetric access properties and relatively small size of network-FIFOs compared to the required peripheral circuitry has led to few such replacements proposed for NoCs. In this paper, we propose control schemes that leverage the "shift-register" nature of spintronic domainwall memory (DWM) to replace conventional memory buffers for the NoC. Our results indicate that the best shift-based scheme utilizes a dual-nanowire approach to ensure that reads and writes can be more effectively aligned with access ports for simultaneous access in the same cycle. Our approach provides a 2.93X speedup over a DWM buffer using a traditional FIFO memory control scheme with a 1.16X savings in energy. Compared to a SRAM-FIFO it exhibits an 8% message latency degradation versus a 56% energy reduction. The resulting approach achieves a 53% reduction in energy delay product compared to SRAM and a 42% reduction in energy delay product versus STT-MRAM.

show abstract

Section: Experimental Methodologymentioning

confidence: 99%

“…STT-MRAM writes are also optimistically assumed to be a single cycle [15] similar to SRAM, while Racetrack shifts and writes take half a cycle allowing a Racetrack to conservatively write and shift, or shift twice in a cycle [24]. The detailed architecture parameters are shown in Table 2.…”

Section: Experimental Methodologymentioning

confidence: 99%

Domain-wall memory buffer for low-energy NoCs

Kline

Melhem

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…In Section 5, we compare our predictive techniques with lazy and eager policies and show that these two policies result in significant slow-down in DWM register file. STAG [25] exploits DWM in memory hierarchy of GPGPUs. To reduce number of shifts in DWM, STAG uses a stride predictor to predict the cache blocks to be accessed in future.…”

Section: Related Workmentioning

confidence: 99%

Reducing shift penalty in Domain Wall Memory through register locality

Atoofian¹

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

View full text Add to dashboard Cite

General-purpose graphics processing units (GPGPUs) have the ability to execute hundreds to thousands of threads simultaneously. Extreme multithreading requires a large register file to hold state of executing threads and facilitate context switching. As feature size reduces, power consumption in the large register file becomes a major concern.In this work, we exploit Domain Wall Memory (DWM) which is a spin-based memory to reduce power consumption in register file. DWM is a promising technology and offers non-volatility, high energy efficiency, and high density by storing several bits into the domains of a ferromagnetic wire. However, despite of favourable properties of DMW over SRAM technology, DWM poses a unique challenge that the bits must be accessed serially through shift operations, leading to variable and potentially higher access latencies. To address this challenge, we propose a new predictive shift policy. In this policy, we exploit register locality across threads and predict source and destination operands of instructions. We record history of registers accessed by instructions and shift magnetic domains of DWM tracks for subsequent instructions, speculatively. Over a wide range of applications from NVIDIA CUDA SDK, ISPASS, and Rodinia, our predictive scheme achieves dramatic energy saving over an SRAM register file while changing performance negligibly.

show abstract

“…Request permissions from Permissions@acm.org. age or graph processing [6,7], AES platform [8] and energy efficient caches [9,10].…”

Section: Introductionmentioning

confidence: 99%

Optimizing data placement for reducing shift operations on domain wall memories

Chen

Sha

Zhuge

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

View full text Add to dashboard Cite

Domain Wall Memory (DWM) using nanowire with data access port, exhibits extraordinary high density, low power leakage, and low access latency. These properties enable DWM to become an attractive candidate for replacing traditional memories. However, data accesses on DWM may require multiple shift operations before the port points to requested data, resulting in varying access latencies. Data placement, therefore, has a significant impact on the performance of data accesses on DWM. This paper studies compiler-based optimization techniques for data placement on DWM. To the authors' best knowledge, this is the first work addressing data placement problem on DWM. We present an efficient heuristic, called Grouping-Based Data Placement (GBDP), for the data placement problem of a given data access sequence on DWM. The experimental results show that GBDP has a significant performance improvement; for example, GBDP reduces 82% shift operations on an 8-port DWM compared with non-optimized approach.

show abstract

STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies

Cited by 19 publications

References 25 publications

Domain-wall memory buffer for low-energy NoCs

Domain-wall memory buffer for low-energy NoCs

Reducing shift penalty in Domain Wall Memory through register locality

Optimizing data placement for reducing shift operations on domain wall memories

Contact Info

Product

Resources

About