Standard Cell Like Via-Configurable Logic Block for Structured ASICs

Abstract

A structured ASIC has some arrays of prefabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a structured ASIC fabric. Our structured ASIC fabric with programmable metals for routing achieves a delay of 2.7 times, an area of 3 times, and a power of 1.5 times that attained by the designs using a commercial cell library.

Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow

“…Recently, Baek et al [43] proposed using selective pattern masks to customize CLBs into different logic functions. In the past, we proposed a VCLB whose layout design tailored to address some issues discussed in Section II-B [10]. This paper is partially based on this previous work.…”

“…Unified Sequential and Combinational VCLB: This is about the capability of configuring the same transistors into combinational logic functions or a flip-flop [7], [10], [36], [45]. Such a capability enables us to save chip area.…”

“…In terms of cell and routing configurability, as shown in Fig. 1, we can define a design style programmability spectrum [10]. One end of the spectrum is the cell-based ASIC with non-programmable cells and metal programmable routing fabrics.…”

Lithography analysis of via-configurable transistor-array fabrics

“…In VCLB approach, distances are not exact multiples, as can be seen in Fig. 1(c) [12]. Thus, adjusting lines to a common pitch may imply significant area penalty.…”

“…Metal1 and polysilicon masks based on (a) VCTA [10], (b) VCC (up) and INVA (down)[11], (c) VCLB[12]. Comparison between drawn layout (a) and lithography simulation (b) of pattern samples.…”