Static Superelement Technique based Macromodeling for High Speed Nano Designs

Abstract

This paper presents a model order reduction technique based on static super-element technique for high speed coupled integrated circuit interconnects in nanometer designs. The salient feature of this technique is less complexity in computation of a few smallest poles of the reduced order model. This paper shows that the static super-element technique produces reduced systems that accurately follow the time and frequency-domain responses of the original system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed technique achieves more accuracy with less CPU time than the other model order reduction techniques existing in literature.