Stimulus generator for SEIR method based ADC BIST

Abstract

Testing of ADC in SOC is a significant challenge since it usually has no connection to the outside. Built-in self-test (BIST) is regarded as a promising alternative to traditional test. Most reported ADC BIST research works try to replicate a production test scheme on chip. This approach requires input ramp with high linearity which is hard to achieve on chip. This paper investigates signal generator implementation issues of adapting stimulus error identification and removal method which was presented for production test into a practical ADC BIST solution. A stimulus generator using very small transistor count is presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that generated signals with less than 7 bits linearity, together with the simple level shifts, are able to test a 16-bit ADC to 16 bit accuracy level. These results demonstrate that accurate BIST of deeply embedded AMS blocks may be practically implemented on chip with very low overhead.

Built-in self-test and self-calibration for analog and mixed signal circuits

“…will be slightly smaller but the conclusion in (5.12) and (5.13) are still valid. (54) and (70), the shift generators are independent, but the structure of the BIST is relatively more complicated, consuming more power and requiring more design efforts. To eliminate the dependency on the ADC architecture, an independent low-power shift generator with simple structure is a better choice for on-chip implementation.…”

Linearity testing of ADCs using low linearity stimulus and Kalman filtering

“…Two sets of histogram counts, C 1 and C 2 , , are obtained from R 1 and R 2 respectively. For a detailed working of the algorithms refer to [3] and [4].Simple signal generators described in [7] can be used to generate the stimuli.…”

“…The low linearity stimulus used for simulations is 7-bit linear, generated from simulations of signal generator circuit suggested in [7]. The ADC that has been used for simulation is a 14-bit flash type ADC.…”

Signal generators for cost effective BIST of ADCs

“…For FRE based SEIR testing used in this work, it can be shown that for a small shift, the algorithmic error in estimating the INL of the ADC will be bounded by 0.25LSB if the following condition [4] is satisfied:…”

“…The challenge of generating highly linear or spectrally pure stimulus signals with a very small die area is one of the biggest challenges in developing practical methods for Built in Self Test (BIST) of ADCs [4]- [5]. For this reason, quasi static linearity BIST of even a 12-bit ADC is almost never attempted in commercial products.…”