Study and VHDL implementation of a novel chaos-based block cipher algorithm for digital image security

Abstract

We live in an interconnected world, and digital data transmissions have reached significant importance as they are the most used means of communication. Connected objects are widely used in our digital life, yet they may pose vulnerabilities and risks such as hacking or personal data theft due to their often inadequate security. In response to the size and capability restrictions of many existing embedded devices, lightweight cryptography has been considered. This article describes a hardware implementation of the lightweight cryptographic method [very high speed integrated circuit hardware description language (VHDL) and field-programmable gate arrays (FPGAs)]. This work presents a hardware solution for securing digital information, more specifically images, and to ensure a high level of security and favorable performance, a robust algorithm with respect to Shannon's theory, Chaos, and its hardware implementation. The algorithm is a block cipher scheme that treats a block of 128-bit length. The paper discusses the method's two main parts: the key generator-based chaos and the block cipher algorithm that consists of a whitening operation, random permutation, and key-dependent S-box. Both the key generator and the encryption algorithm are implemented using VHDL language on a Xilinx ZedBoard Zynq Development Kit platform. The generated key sequences are tested using the NIST SP 800-22 test suite. The hardware implementation of the proposed algorithm is capable of securing different gray-scale images while maintaining low power usage, a good frequency of 129.9038 MHz, and a high throughput of 1651.201 Mbps. Both statistical and differential attacks demonstrate that the cryptosystem is capable of effective security against the next generation of cryptographic attacks.