Study of substrate noise and techniques for minimization

Abstract

This thesis presents a study of the effects of substrate noise on analog circuits in mixedsignal chips and techniques for minimizing these harmful effects on sensitive analog circuits. A microchip built in a 0.25um CMOS epitaxial process was designed, fabricated, and tested for this research.Through the use of an on-chip sampling scope, the effect of substrate noise generated by digital inverters with coupling capacitors to the substrate on analog circuits was characterized. Substrate noise coupled into a representative analog circuit, a switched capacitor delta-sigma modulator primarily through the asymmetrical parasitics of the input sampling circuit. Furthermore, since some of the parasitics are nonlinear with input voltage, substrate noise couples into the analog circuits producing an input signal dependent component and an input signal independent component. The substrate noise, with decay time constants of a few nanoseconds and ringing frequencies of few hundred megahertz, can decrease analog circuit performance. In the case of a delta-sigma modulator, substrate noise caused the signal to noise power ratio to decrease by more than 18dB, 3 bits in terms of analog-to-digital converter metrics.In addition, two techniques of minimizing the substrate noise and its effects were explored. The first used a replica delta-sigma modulator on the same chip to subtract the effects of substrate noise from the original delta-sigma modulator. This method proved useful for removing input signal independent substrate noise, but not input signal dependent substrate noise which dominates in-band noise for large input signal magnitudes.The second technique involved an active substrate noise cancellation system. A discrete time feedback loop senses the substrate noise, processes it through a filter, and uses an array of digital inverters to cancel the substrate noise. The principal advantages of this technique are the shaping of substrate noise through a designed filter without a significant power penalty and design independence from the analog and digital components. Measured data shows that this technique is capable of over 20dB reduction in substrate noise on the substrate voltage itself. Measured data also shows over 10dB improvement in SNDR of the delta-sigma modulator in certain cases.

Multi-Channel Audio CODEC with Channel Interference Suppression

“…The channel interference suppressor occupies 0.2 mm 2 and consumes 0.3 mW power, which is 9% and 3% overheads in terms of area and power, respectively. As compared to the conventional substrate noise shaping [4] and PSRR enhancement [8] techniques showing 10 dB and 22 dB improvements, respectively, the proposed multi-channel audio CODEC with novel interference suppression can provide far better performance (43 dB in terms of SNR and 45 dB in terms of SNDR) for minimizing the total interference noise, and is very suitable for multi-channel configuration.…”

“…Increased switching noise in a multi-channel audio CODEC may invoke input-dependent harmonic components with increased noise floor in frequency spectrum, resulting in system performance degradation [4][5][6]. Especially, the sampled values of the sampling circuits in channels having different clock frequencies are mutually affected by channel interference due to audible inter-modulated tone noises, which cannot be avoided by a simple phase adjustment.…”

“…Design techniques to just handle a single type of interference noise coupled through the substrate [4], shared supply voltage, or reference voltage have only been studied, [7][8][9]. An active substrate noise shaping [4] was used to minimize the switching noise by sensing and cancelling the switching signals coupled into the substrate. This technique can actively minimize the performance degradation due to substrate noise but incur an overhead in terms of power and area.…”

Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications

“…Concerning noise, PDM also lowers switching activity during A/D conversion, causing less digital noise injection in the FPA. Switching noise mainly arises in the substrate and propagates through circuit asymmetries over the pixel sensor [109]. The presence of perturbations on power supply nodes, either at routing or substrate level, are reflected in higher σ 2 integ,ir and σ 2 ADC,ir values of (1.14).…”

An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell Technology

“…Recently, the effects of the substrate noise from digital circuits to analog circuits have been studied actively [10]- [12]. As the access speed of the SRAM is raised more and more, the effect of the substrate noise from control and decoding circuits to cells can not be ignored.…”