Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET

Barman, Kuheli Roy; Baishya, Srimanta

doi:10.1007/s12633-020-00561-8

Cited by 10 publications

(4 citation statements)

References 56 publications

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“…Harmonic distortion is one of the challenges in communication systems, and understanding the influence of spacers on higher order harmonics is essential. 44…”

Section: Ananlog/rf and Linearity Resultsmentioning

confidence: 99%

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Sreenivasulu

Narendar

2021

ECS J. Solid State Sci. Technol.

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Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. The Si NS MOSFETs provide high current drivability due to wider effective channel (W eff) and maintain better short channel performance. Here, the performance of junctionless (JL) SOI NS p-MOSFET is evaluated by invoking HfxTi1−xO2 gate stack to overcome adverse short channel effects (SCEs). The device performance is enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on I ON/I OFF, SS, V th is presented and the analog/RF metrics of the device are evaluated. The power consumption, dynamic power, and static power analyses of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an I ON/I OFF ratio of more than ∼106 with NS widths of 10 to 30 nm, respectively. The device exhibits better performance (I ON) with higher NS widths and ensures potential towards high-performance applications. However, with an increase in NS widths the threshold voltage (V th) tends to downfall and leads to deterioration in subthreshold performance . With high-k spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

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“…Harmonic distortion is one of the challenges in communication systems, and understanding the influence of spacers on higher order harmonics is essential. 44…”

Section: Ananlog/rf and Linearity Resultsmentioning

confidence: 99%

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Sreenivasulu

Narendar

2021

ECS J. Solid State Sci. Technol.

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“…Nanoscale transistors are used in a wide variety of elds like communication, automobiles, medical equipment, analog and digital integrated circuits, sensing applications and power electronics. As per the requirement, the nano transistors are used at different temperatures and are crucial to analyze the performance of transistors at various ranges of temperatures [35].…”

Section: Impact Of Temperature and Work Function Variations On Nsfetmentioning

confidence: 99%

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Neelam

Prithvi

2022

Silicon

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Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical con gurations of the NSFET. In this script, DC performance of 3D GAA NSFET is analyzed by varying the width, thickness of the device. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm, and 10 to 50 nm respectively to analyse the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (I ON ), off current (I OFF ), switching ratio (I ON /I OFF ), threshold voltage (V th ) and drain induced barrier lowering (DIBL) are studied. On top of that, the device's electrical characteristics are analyzed for a wide range of temperatures from -43 o C to 127 o C to identify the temperature compensation point and is observed at V GS = 0.55 V and I D = 3.86 × 10 −6 A. Furthermore, the important process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses tell that, for sub -7 nm, the NSFET is a potential device for high performance and good logic applications.

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“…In our previous articles, we have reported the noise characteristics of a VSTB FET 11,12 . In addition, the effect of temperature and architectural parameters on the DC, analog/RF parameters of this new device was also investigated 12,26 . Further, it is well established that excessive thinning of gate oxide causes a severe increase in gate leakage current and degrades device performance.…”

Section: Introductionmentioning

confidence: 99%

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Barman

Baishya

2021

Int J RF Microw Comput Aided Eng

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This article reports the DC and analog/radio frequency (RF) response of a newly invented device called vertical super‐thin body (VSTB) FET towards high‐k (Si3N4/HfO2) and low‐k (SiO2) gate dielectrics in conjunction with the scaling effect through a well‐calibrated Sentaurus TCAD tool. At channel length (LG) of 20 nm, compared to SiO2, Si3N4 improves various DC parameters such as off‐state leakage current (Ioff), on‐current (Ion), on‐to‐off current ratio (Ion/Ioff ratio), subthreshold swing (SS), and drain‐induced‐barrier‐lowering (DIBL) by 77.15%, 26.2%, one order of magnitude, 15.78%, and 36.2%, respectively. On the other hand, a higher improvement is seen in all these DC parameters for the HfO2 gate dielectric (Ioff, Ion, Ion/Ioff ratio, SS, DIBL improves respectively by 91.8%, 41.57%, two orders of magnitude, 28.28%, and 62.71%). The underlying physics behind such excellent improvement is explained by the device off‐state energy band diagram, electrostatic potential, and channel electron density profile for each dielectric. Further, for all the gate dielectrics considered, the device characteristics were studied for a wide range of LG from 10 to 50 nm to reveal the scaling impact on the device performance. Irrespective of the gate dielectric material, the device exhibits excellent performance at LG = 10 nm, which in turn indicates to the brilliant scalability of this new device. Besides, although Si3N4 and HfO2 increase gate capacitance (Cgg)/gate‐drain capacitance (Cgd), due to the extremely low values of Cgg/Cgd, enhanced unit gain cut‐off frequency, and gain‐bandwidth‐product is achieved. In addition, the increased transconductance (gm) of the device applying Si3N4/HfO2 gate dielectric leads to a higher peak value of TGF, intrinsic gain, TFP, GFP, and GTFP. This study intends to expand the fundamental knowledge about such a new device as a VSTB FET and hence, aims to be utilized in the future research of this novel device.

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Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET

Cited by 10 publications

References 56 publications

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

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