Study on the Development of the Chip Information Industry Based on Moore’s Law

Zeng, Guowang; Zeng, Shihong

doi:10.4236/jcc.2017.514004

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…Since the invention of the first integrated circuit (IC) in 1958, planar metal-oxide semiconductor field-effect transistors (MOSFETs) based on silicon have been dominating in the global microelectronics industry and continuously used to build electronic devices, such as modern microprocessors, which up-to-date can integrate more than one billion transistors on a single chip 1–3 . The raised challenges following this microelectronic revolution are still how to fabricate the transistors more efficiently by keeping the smallest possible footprint and how to better exploit the devices containing billions of transistors.…”

Section: Introductionmentioning

confidence: 99%

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah

Feng

Strempel

et al. 2019

Sci Rep

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This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p -channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage ( V th ) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al 2 O 3 ) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (Δ V th ) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

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Section: Introductionmentioning

confidence: 99%

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah

Feng

Strempel

et al. 2019

Sci Rep

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Nucleation and growth mechanism for atomic layer deposition of Al2O3 on two-dimensional WS2 monolayer

Lee

Chiranjeevulu

Sireesha

et al. 2022

Journal of Vacuum Science &Amp; Technology A

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Nanoelectronics holds significant promise for two-dimensional (2D) semiconducting transition metal dichalcogenide (TMD) applications. On a polycrystalline WS2 monolayer created by metal-organic chemical vapor deposition (MOCVD) at 950 °C, we studied the nucleation, growth, and development of Al2O3 atomic layer deposition (ALD) on a SiO2/Si substrate. In this investigation, we used various complementary characterization methods, such as Raman spectroscopy, elastic recoil detection, atomic force microscopy, and time-of-flight secondary ion mass spectrometry, to understand thoroughly the intrinsic reactivity of WS2. Strong peak intensity changes at the interfaces in the Raman line scans of the SiO2/Si patterns suggest extremely crystalline WS2. After multiple ALD cycles, triangular WS2 crystals were decorated to provide a two-dimensional growth mode with a great selectivity for grain boundaries and step edges. The results of this work can be used for further exploration of the TMD monolayer structure and properties, which is essential for tailoring 2D materials for a specific application in devices.

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Study on the Development of the Chip Information Industry Based on Moore’s Law

Abstract: Chips are the carriers of ICs (integrated circuits). As a result of design, manufacturing, and packaging and testing processes, chips are typically wholly independent entities intended for immediate use.

Cited by 2 publications

References 5 publications

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Nucleation and growth mechanism for atomic layer deposition of Al2O3 on two-dimensional WS2 monolayer

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