Study on the Solution of via Bottom Void in 90nm Technology

Abstract

Via bottom void is one of the problems related to the metal interconnections in semiconductor devices. In 0.13μm technology, Novellus Sabre serial is wildly applied as copper(Cu) electro chemical plating (ECP) tool, but the problem of high hit ratio of via bottom void in 90nm CMOS technology makes it difficult to perform as well as in the 0.13μm technology. In this paper, the mechanism of the formation of via bottom void of Cu interconnection was analyzed and the solution of the problem in the 90nm technology was studied. A series of experiments were carried out and the result shown that the via bottom void can be eliminated by increasing the plating current during the initial period of Cu plating process.